Hi Prabhakar,
Thank you for the patch.
On Fri, Aug 07, 2020 at 06:49:52PM +0100, Lad Prabhakar wrote:
> Add du node to r8a7742 SoC DT. Boards that want to enable the DU
> need to specify the output topology.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu
> <marian-cristian.rotariu...@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
> ---
> arch/arm/boot/dts/r8a7742.dtsi | 35 ++++++++++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
> index 4a8d27dff9f7..a979a4b3de61 100644
> --- a/arch/arm/boot/dts/r8a7742.dtsi
> +++ b/arch/arm/boot/dts/r8a7742.dtsi
> @@ -1509,6 +1509,41 @@
> resets = <&cpg 408>;
> };
>
> + du: display@feb00000 {
> + compatible = "renesas,du-r8a7742";
> + reg = <0 0xfeb00000 0 0x70000>;
> + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
> + <&cpg CPG_MOD 722>;
> + clock-names = "du.0", "du.1", "du.2";
> + resets = <&cpg 724>;
> + reset-names = "du.0";
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + du_out_rgb: endpoint {
> + };
> + };
> + port@1 {
> + reg = <1>;
> + du_out_lvds0: endpoint {
> + };
> + };
> + port@2 {
> + reg = <2>;
> + du_out_lvds1: endpoint {
> + };
> + };
> + };
> + };
> +
> prr: chipid@ff000044 {
> compatible = "renesas,prr";
> reg = <0 0xff000044 0 4>;
--
Regards,
Laurent Pinchart
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