On Fri, Jun 05, 2020 at 12:03:19AM +0300, Ville Syrjälä wrote:
> On Thu, Jun 04, 2020 at 08:01:03PM +0000, Almahallawy, Khaled wrote:
> > On Thu, 2020-06-04 at 22:06 +0300, Ville Syrjälä wrote:
> > > On Thu, Jun 04, 2020 at 10:33:48AM +0530, Vidya Srinivas wrote:
> > > > Signed-off-by: Khaled Almahallawy <khaled.almahall...@intel.com>
> > > > Signed-off-by: Vidya Srinivas <vidya.srini...@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 40
> > > > ++++++++++++++++++++++++++-------
> > > > 1 file changed, 32 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 7223367171d1..44663e8ac9a1 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct
> > > > intel_dp *intel_dp)
> > > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port-
> > > > >base.base.crtc);
> > > > enum pipe pipe = crtc->pipe;
> > > > - u32 trans_ddi_func_ctl_value, trans_conf_value,
> > > > dp_tp_ctl_value;
> > > > + u32 trans_ddi_func_ctl_value, trans_conf_value,
> > > > dp_tp_ctl_value, trans_ddi_port_mask;
> > > > + enum port port = intel_dig_port->base.port;
> > > > + i915_reg_t dp_tp_reg;
> > > > +
> > > > + if (IS_ELKHARTLAKE(dev_priv)) {
> > > > + dp_tp_reg = DP_TP_CTL(port);
> > > > + trans_ddi_port_mask = TRANS_DDI_PORT_MASK;
> > > > + } else if (IS_TIGERLAKE(dev_priv)) {
> > > > + dp_tp_reg = TGL_DP_TP_CTL(pipe);
> > > > + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK;
> > > > + }
> > > >
> > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv,
> > > > TRANS_DDI_FUNC_CTL(pip
> > > > e));
> > > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
> > > > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
> > > >
> > > > + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg);
> > > > trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
> > > > - TGL_TRANS_DDI_PORT_MASK);
> > > > + trans_ddi_port_mask);
> > > > trans_conf_value &= ~PIPECONF_ENABLE;
> > > > dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
> > > >
> > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
> > > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
> > > > trans_ddi_func_ctl_value);
> > > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
> > > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value);
> > >
> > > All this ad-hoc modeset code really should not exist. It's going to
> > > have different bugs than the norma modeset paths, so compliance
> > > testing
> > > this special code proves absolutely nothing about the normal modeset
> > > code. IMO someone needs to take up the task of rewrtiting all this to
> > > just perform normal modesets.
> >
> > Agree. I've just found that we get kernel NULL pointer dereference and
> > panic when we try to access to_intel_crtc(intel_dig_port-
> > >base.base.crtc).
>
> Yeah, that's a legacy pointer which should no longer be used at all
> with atomic drivers. I'm slowly trying to clear out all this legacy
> cruft. The next step I had hoped to take was
> https://patchwork.freedesktop.org/series/76993/ but then this
> compliacnce stuff landed and threw another wrench into the works.
We had several discussions on design of DP PHY compliance and the patches were
on the M-L
for quite some time without anyone giving feedback on the actual design of
whether they should
happen through modeset or directly from the PHY comp request short pulse.
My first feedback was also that this should happen through a complete modeset
where after we get
PHY comp request we send a uevent like we do for link layer compliance and then
trigger a full modeset.
But honestly that was just a lot of overhead and
The reason we decided to go with this ad hoc approach was that with PHY
compliance request,
nothing really changes in terms of link parameters so we do not need to go
through
a complete modeset request unlike link layer compliance where we need to do
compute config
all over again to do the link params computation.
Every PHY comp request first sends a link layer comp request that does a full
modeset
and sets up the desired link rate/lane count.
Then with PHY request, all we need to do is disable pipe conf, dp_tp_ctl, set
the PHY patterns
and renable the pipe conf and dp_tp_ctl without interfering and doing anything
with a full modeset.
Now i think if we need to scale this to other platforms, can we add a per
platform hook
for handle_phy_request that gets the correct DP_TP_CTL etc and sets up the PHY
patterns and
reenables the already set link?
We have thoroughly tested this using the scopes and DPR 100 and it has been
working correctly
with the existing IGT compliance tool so IMO no need to rewrite the entire set
of patches.
Ville, Khaled ?
Regards
Manasi
>
> --
> Ville Syrjälä
> Intel
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