[PATCH 1/1] ARM: dts: novena: Add LVDS-to-eDP bridge bindings

[srk]

From: Marek Vasut <ma...@denx.de>

Add bindings for the LVDS-to-eDP bridge chip, IT6251, which is
used to connect the standard 1920x1080 panel on Novena laptop.

Tested on a Kosagi Novena laptop with imx6 display controller.

Based on v5.7-rc2, applies to drm-misc-next 5e6ed29d72d2

Signed-off-by: Marek Vasut <ma...@denx.de>
Signed-off-by: Richard Marko <s...@48.io>
Cc: Fabio Estevam <fabio.este...@nxp.com>
Cc: Shawn Guo <shawn...@kernel.org>
---
 arch/arm/boot/dts/imx6q-novena.dts | 57 +++++++++++++++++++++++++++++-
 1 file changed, 56 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6q-novena.dts 
b/arch/arm/boot/dts/imx6q-novena.dts
index 69f170ff31c5..803a97e04dc4 100644
--- a/arch/arm/boot/dts/imx6q-novena.dts
+++ b/arch/arm/boot/dts/imx6q-novena.dts
@@ -109,6 +109,12 @@ heartbeat {
        panel: panel {
                compatible = "innolux,n133hse-ea1";
                backlight = <&backlight>;
+
+               port {
+                       panel_in_edp0: endpoint {
+                               remote-endpoint = <&bridge_out_edp0>;
+                       };
+               };
        };
 
        reg_2p5v: regulator-2p5v {
@@ -146,6 +152,7 @@ reg_display: regulator-display {
                startup-delay-us = <200000>;
                gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>;
                enable-active-high;
+               regulator-always-on;
        };
 
        reg_lvds_lcd: regulator-lvds-lcd {
@@ -155,6 +162,7 @@ reg_lvds_lcd: regulator-lvds-lcd {
                regulator-max-microvolt = <3300000>;
                gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
                enable-active-high;
+               regulator-always-on;
        };
 
        reg_pcie: regulator-pcie {
@@ -212,6 +220,17 @@ &audmux {
        status = "okay";
 };
 
+&clks {
+       assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+                         <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+                         <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
+                         <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
+       assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+                                <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
+};
+
 &ecspi3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_ecspi3_novena>;
@@ -423,6 +442,29 @@ codec: es8328@11 {
                                         <&clks IMX6QDL_CLK_CKO1_PODF>;
                assigned-clock-rates = <0 0 722534400 22579200>;
        };
+
+       it6251@5c {
+               compatible = "ite,it6251";
+               reg = <0x5c>, <0x5e>;
+               reg-names = "bridge", "lvds";
+               power-supply = <&reg_display>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_lvdsbridge_novena>;
+
+               ports {
+                       port@0 {
+                               bridge_out_edp0: endpoint {
+                                       remote-endpoint = <&panel_in_edp0>;
+                               };
+                       };
+
+                       port@1 {
+                               bridge_in_lvds0: endpoint {
+                                       remote-endpoint = <&lvds0_out>;
+                               };
+                       };
+               };
+       };
 };
 
 &kpp {
@@ -443,6 +485,14 @@ lvds-channel@0 {
                fsl,data-width = <24>;
                fsl,panel = <&panel>;
                status = "okay";
+
+               port@4 {
+                       reg = <4>;
+
+                       lvds0_out: endpoint {
+                               remote-endpoint = <&bridge_in_lvds0>;
+                       };
+               };
        };
 };
 
@@ -529,10 +579,15 @@ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS           0x130b0
                >;
        };
 
+       pinctrl_lvdsbridge_novena: lvdsbridgegrp-novena {
+               fsl,pins = <
+                       MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28       0x1b0b1
+               >;
+       };
+
        pinctrl_backlight_novena: backlightgrp-novena {
                fsl,pins = <
                        MX6QDL_PAD_DISP0_DAT8__PWM1_OUT         0x1b0b0
-                       MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28       0x1b0b1
                        MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b1
                >;
        };
-- 
2.25.1

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