On Tue, 24 Dec 2019 15:38:51 +0100, Miquel Raynal wrote: > PX30 SoCs use a single PHY shared by two display pipelines: MIPI DSI > and LVDS. In the case of the LVDS IP, document the possibility to fill > a PHY handle. > > Signed-off-by: Miquel Raynal <miquel.ray...@bootlin.com> > --- > .../devicetree/bindings/display/rockchip/rockchip-lvds.txt | 3 +++ > 1 file changed, 3 insertions(+) >
Acked-by: Rob Herring <r...@kernel.org> _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
