External memory controller is interconnected with memory controller and
with external memory. Document new interconnect property which designates
external memory controller as interconnect provider.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
.../bindings/memory-controllers/nvidia,tegra124-emc.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.txt
b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.txt
index ba0bc3f12419..ff48b46604e6 100644
---
a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.txt
+++
b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.txt
@@ -5,6 +5,7 @@ Required properties :
- compatible : Should be "nvidia,tegra124-emc".
- reg : physical base address and length of the controller's registers.
- nvidia,memory-controller : phandle of the MC driver.
+- #interconnect-cells : Should be 1.
The node should contain a "emc-timings" subnode for each supported RAM type
(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address
@@ -195,6 +196,8 @@ Example SoC include file:
reg = <0x0 0x7001b000 0x0 0x1000>;
nvidia,memory-controller = <&mc>;
+
+ #interconnect-cells = <1>;
};
};
--
2.23.0
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