On 2019-11-11 8:29 p.m., Bjorn Helgaas wrote: > From: Bjorn Helgaas <bhelg...@google.com> > > Add definitions for these PCIe Link Control 2 register fields: > > Enter Compliance > Transmit Margin > > and use them in amdgpu and radeon. > > NOTE: This is a functional change because "7 << 9" was apparently a typo. > That mask included the high order bit of Transmit Margin, the Enter > Modified Compliance bit, and the Compliance SOS bit, but I think what > was intended was the 3-bit Transmit Margin field at bits 9:7.
Can you split out the functional change into a separate patch 1? That could make things easier for anyone who bisects the functional change for whatever reason. -- Earthling Michel Dänzer | https://redhat.com Libre software enthusiast | Mesa and X developer _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
