On Sun, Oct 20, 2019 at 08:21:32PM +0200, Hans de Goede wrote:
> Fastboot is not working on an Asus T100HA, it gives the following
> relevant messages / errors:
>
> dsi pll div 000201e6, ctrl 80080100
> fastset mismatch in dsi_pll.ctrl (expected 0x80100100, found 0x80080100)
> fastset mismatch in dsi_pll.div (expected 0x0002008e, found 0x000201e6)
>
> The problem seems to be that the GOP picks 5 for the P divisor, where as
> we end up picking 4.
>
> This commit fixes this by first checking of the currently configured
> DSI PLL settings match the desired pclk and if they do, stick with
> the currently configured PLL settings.
>
> Note that vlv_dsi_get_pclk() stores the read ctrl and div values inside
> config->dsi_pll, so they are set to the GOP / previous values after
> calling it.
>
> Signed-off-by: Hans de Goede <hdego...@redhat.com>
> ---
> drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 26 +++++++++++++++-------
> 1 file changed, 18 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> index 95f39cd0ce02..4a09edecd597 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> @@ -119,15 +119,25 @@ int vlv_dsi_pll_compute(struct intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> int ret;
> - u32 dsi_clk;
> -
> - dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
> - intel_dsi->lane_count);
> + u32 dsi_clk, current_pclk;
>
> - ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
> - if (ret) {
> - DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
> - return ret;
> + /*
> + * For exact matches, the GOP may pick another set of divisors
> + * then we do, if the GOP settings are an exact match keep them.
> + */
> + current_pclk = vlv_dsi_get_pclk(encoder, config);
One is not allowed to touch the hw in .compute_config().
The question is why does the GOP generate a different P divider?
Does it use a slightly different clock?
> + if (current_pclk == intel_dsi->pclk) {
> + config->dsi_pll.ctrl &= DSI_PLL_P1_POST_DIV_MASK;
> + } else {
> + dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk,
> + intel_dsi->pixel_format,
> + intel_dsi->lane_count);
> +
> + ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
> + if (ret) {
> + DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
> + return ret;
> + }
> }
>
> if (intel_dsi->ports & (1 << PORT_A))
> --
> 2.23.0
--
Ville Syrjälä
Intel
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