[PATCH 1/2] drm: add cache support for arm64

[Rob Clark]

From: Rob Clark <robdcl...@chromium.org>

This will let drm/msm stop abusing DMA API for cache ops, at least for
arm64.

Signed-off-by: Rob Clark <robdcl...@chromium.org>
---
 arch/arm64/mm/flush.c       |  2 ++
 drivers/gpu/drm/drm_cache.c | 20 +++++++++++++++++---
 include/drm/drm_cache.h     |  4 ++++
 3 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c
index dc19300309d2..f0eb6320c979 100644
--- a/arch/arm64/mm/flush.c
+++ b/arch/arm64/mm/flush.c
@@ -93,3 +93,5 @@ void arch_invalidate_pmem(void *addr, size_t size)
 }
 EXPORT_SYMBOL_GPL(arch_invalidate_pmem);
 #endif
+
+EXPORT_SYMBOL_GPL(__flush_dcache_area);
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 3bd76e918b5d..90105c637797 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -69,6 +69,14 @@ static void drm_cache_flush_clflush(struct page *pages[],
 }
 #endif
 
+#if defined(__powerpc__)
+static void __flush_dcache_area(void *addr, size_t len)
+{
+       flush_dcache_range((unsigned long)addr,
+                          (unsigned long)addr + PAGE_SIZE);
+}
+#endif
+
 /**
  * drm_clflush_pages - Flush dcache lines of a set of pages.
  * @pages: List of pages to be flushed.
@@ -90,7 +98,7 @@ drm_clflush_pages(struct page *pages[], unsigned long 
num_pages)
        if (wbinvd_on_all_cpus())
                pr_err("Timed out waiting for cache flush\n");
 
-#elif defined(__powerpc__)
+#elif defined(__powerpc__) || defined(CONFIG_ARM64)
        unsigned long i;
        for (i = 0; i < num_pages; i++) {
                struct page *page = pages[i];
@@ -100,8 +108,7 @@ drm_clflush_pages(struct page *pages[], unsigned long 
num_pages)
                        continue;
 
                page_virtual = kmap_atomic(page);
-               flush_dcache_range((unsigned long)page_virtual,
-                                  (unsigned long)page_virtual + PAGE_SIZE);
+               __flush_dcache_area(page_virtual, PAGE_SIZE);
                kunmap_atomic(page_virtual);
        }
 #else
@@ -135,6 +142,13 @@ drm_clflush_sg(struct sg_table *st)
 
        if (wbinvd_on_all_cpus())
                pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64)
+       struct sg_page_iter sg_iter;
+
+       for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
+               struct page *p = sg_page_iter_page(&sg_iter);
+               drm_clflush_pages(&p, 1);
+       }
 #else
        pr_err("Architecture has no drm_cache.c support\n");
        WARN_ON_ONCE(1);
diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
index 987ff16b9420..f94e7bd3eca4 100644
--- a/include/drm/drm_cache.h
+++ b/include/drm/drm_cache.h
@@ -40,6 +40,10 @@ void drm_clflush_sg(struct sg_table *st);
 void drm_clflush_virt_range(void *addr, unsigned long length);
 bool drm_need_swiotlb(int dma_bits);
 
+#if defined(CONFIG_X86) || defined(__powerpc__) || defined(CONFIG_ARM64)
+#define HAS_DRM_CACHE 1
+#endif
+
 
 static inline bool drm_arch_can_wc_memory(void)
 {
-- 
2.21.0