Add and use bit definitions for RDREG4F on Dove Armada 510.
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
---
drivers/gpu/drm/armada/armada_510.c | 9 +++++++--
drivers/gpu/drm/armada/armada_hw.h | 10 ++++++++++
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/armada/armada_510.c
b/drivers/gpu/drm/armada/armada_510.c
index 0e91d27921bd..370c422f64e3 100644
--- a/drivers/gpu/drm/armada/armada_510.c
+++ b/drivers/gpu/drm/armada/armada_510.c
@@ -24,8 +24,13 @@ static int armada510_crtc_init(struct armada_crtc *dcrtc,
struct device *dev)
dcrtc->extclk[0] = clk;
- /* Lower the watermark so to eliminate jitter at higher bandwidths */
- armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);
+ /*
+ * Lower the watermark so to eliminate jitter at higher bandwidths.
+ * Disable SRAM read wait state to avoid system hang with external
+ * clock.
+ */
+ armada_updatel(CFG_DMA_WM(0x20), CFG_SRAM_WAIT | CFG_DMA_WM_MASK,
+ dcrtc->base + LCD_CFG_RDREG4F);
/* Initialise SPU register */
writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
diff --git a/drivers/gpu/drm/armada/armada_hw.h
b/drivers/gpu/drm/armada/armada_hw.h
index babfca71c4db..5b1af0cc9f50 100644
--- a/drivers/gpu/drm/armada/armada_hw.h
+++ b/drivers/gpu/drm/armada/armada_hw.h
@@ -88,6 +88,16 @@ enum {
ADV_VSYNC_H_OFF = 0xfff << 0,
};
+/* LCD_CFG_RDREG4F - Armada 510 only */
+enum {
+ CFG_SRAM_WAIT = BIT(11),
+ CFG_SMPN_FASTTX = BIT(10),
+ CFG_DMA_ARB = BIT(9),
+ CFG_DMA_WM_EN = BIT(8),
+ CFG_DMA_WM_MASK = 0xff,
+#define CFG_DMA_WM(x) ((x) & CFG_DMA_WM_MASK)
+};
+
enum {
CFG_565 = 0,
CFG_1555 = 1,
--
2.7.4
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