[PATCH 03/11] drm/meson: Add G12A Support for VPP setup

[Neil Armstrong]

Amlogic G12A needs a different VPP setup code, handle it here.

Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
 drivers/gpu/drm/meson/meson_vpp.c | 51 ++++++++++++++++++-------------
 1 file changed, 29 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/meson/meson_vpp.c 
b/drivers/gpu/drm/meson/meson_vpp.c
index f9efb431e953..8c52a3455ef4 100644
--- a/drivers/gpu/drm/meson/meson_vpp.c
+++ b/drivers/gpu/drm/meson/meson_vpp.c
@@ -112,32 +112,39 @@ void meson_vpp_init(struct meson_drm *priv)
                writel_relaxed(0x20000, priv->io_base + _REG(VPP_DOLBY_CTRL));
                writel_relaxed(0x1020080,
                                priv->io_base + _REG(VPP_DUMMY_DATA1));
-       }
+       } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
+               writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL));
 
        /* Initialize vpu fifo control registers */
-       writel_relaxed(readl_relaxed(priv->io_base + _REG(VPP_OFIFO_SIZE)) |
-                       0x77f, priv->io_base + _REG(VPP_OFIFO_SIZE));
+       if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
+               writel_relaxed(0xfff << 20 | 0x1000,
+                              priv->io_base + _REG(VPP_OFIFO_SIZE));
+       else
+               writel_relaxed(readl_relaxed(priv->io_base + 
_REG(VPP_OFIFO_SIZE)) |
+                               0x77f, priv->io_base + _REG(VPP_OFIFO_SIZE));
        writel_relaxed(0x08080808, priv->io_base + _REG(VPP_HOLD_LINES));
 
-       /* Turn off preblend */
-       writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0,
-                           priv->io_base + _REG(VPP_MISC));
-
-       /* Turn off POSTBLEND */
-       writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
-                           priv->io_base + _REG(VPP_MISC));
-
-       /* Force all planes off */
-       writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND |
-                           VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND |
-                           VPP_VD1_PREBLEND | VPP_VD2_PREBLEND, 0,
-                           priv->io_base + _REG(VPP_MISC));
-
-       /* Setup default VD settings */
-       writel_relaxed(4096,
-                       priv->io_base + _REG(VPP_PREBLEND_VD1_H_START_END));
-       writel_relaxed(4096,
-                       priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
+       if (!meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
+               /* Turn off preblend */
+               writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0,
+                                   priv->io_base + _REG(VPP_MISC));
+
+               /* Turn off POSTBLEND */
+               writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
+                                   priv->io_base + _REG(VPP_MISC));
+
+               /* Force all planes off */
+               writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND |
+                                   VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND |
+                                   VPP_VD1_PREBLEND | VPP_VD2_PREBLEND, 0,
+                                   priv->io_base + _REG(VPP_MISC));
+
+               /* Setup default VD settings */
+               writel_relaxed(4096,
+                               priv->io_base + 
_REG(VPP_PREBLEND_VD1_H_START_END));
+               writel_relaxed(4096,
+                               priv->io_base + 
_REG(VPP_BLEND_VD2_H_START_END));
+       }
 
        /* Disable Scalers */
        writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
-- 
2.21.0

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