Hi,
On Wed, 2019-01-23 at 16:54 +0100, Maxime Ripard wrote:
> The current code allows the TCON clock divider to have a range between 4
> and 127 when feeding the DSI controller.
>
> The only display supported so far had a display clock rate that ended up
> using a divider of 4, but testing with other displays show that only 4
> seems to be functional.
>
> This also aligns with what Allwinner is doing in their BSP, so let's just
> hardcode that we want a divider of 4 when using the DSI output.
>
> Signed-off-by: Maxime Ripard <maxime.rip...@bootlin.com>
Reviewed-by: Paul Kocialkowski <paul.kocialkow...@bootlin.com>
Cheers,
Paul
> ---
> drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++--
> drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 2 ++
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> index 0420f5c978b9..bee73ead732a 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> @@ -341,8 +341,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon
> *tcon,
> u32 block_space, start_delay;
> u32 tcon_div;
>
> - tcon->dclk_min_div = 4;
> - tcon->dclk_max_div = 127;
> + tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
> + tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
>
> sun4i_tcon0_mode_set_common(tcon, mode);
>
> diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
> b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
> index dbbc5b3ecbda..6d4a3c0fd9b5 100644
> --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
> +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
> @@ -13,6 +13,8 @@
> #include <drm/drm_encoder.h>
> #include <drm/drm_mipi_dsi.h>
>
> +#define SUN6I_DSI_TCON_DIV 4
> +
> struct sun6i_dphy {
> struct clk *bus_clk;
> struct clk *mod_clk;
--
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
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