Hello! On 17.01.2019 4:49, Laurent Pinchart wrote:
On the D3 and E3 SoCs the LVDS encoder has an extended internal PLL and supplies a clock to the DU. That clock is used not only for the LVDS outputs but also for the DPAD output. The LVDS encoder thus needs to be available to the DU even when its output is disabled. Don't fail probe in that cose on D3 and E3.
Case?
Signed-off-by: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com>
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