From: Sven Van Asbroeck <sven...@arcx.com>
We used an oscilloscope to observe the actual polarity of the
DI's pixel clock, and saw the following:
DI_GENERAL bit 17 is SET:
pixel data is stable on the pixel clock's FALLING edge
DI_GENERAL bit 17 is CLEAR:
pixel data is stable on the pixel clock's RISING edge
However, the current driver configures the exact opposite of the
behaviour documented in video/imx-ipu-v3.h:
unsigned clk_pol:1; /* true = rising edge */
Fixes: 85de9d17c485c4196f74 ("imx-drm: match ipu_di_signal_cfg's clk_pol with
its description.")
Signed-off-by: Sven Van Asbroeck <sven...@arcx.com>
---
drivers/gpu/ipu-v3/ipu-di.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c
index d2f1bd9d3deb..f296fa461875 100644
--- a/drivers/gpu/ipu-v3/ipu-di.c
+++ b/drivers/gpu/ipu-v3/ipu-di.c
@@ -619,7 +619,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct
ipu_di_signal_cfg *sig)
if (sig->mode.flags & DISPLAY_FLAGS_VSYNC_HIGH)
di_gen |= ipu_di_gen_polarity(sig->vsync_pin);
- if (sig->clk_pol)
+ if (!sig->clk_pol)
di_gen |= DI_GEN_POLARITY_DISP_CLK;
ipu_di_write(di, di_gen, DI_GENERAL);
--
2.17.1
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