Hi, Bibby:
On Wed, 2018-09-05 at 16:31 +0800, Bibby Hsieh wrote:
> From: chunhui dai <chunhui....@mediatek.com>
>
> The default timing of DPI data and clock is not match.
> We could adjust this bit to make them match.
>
> Signed-off-by: chunhui dai <chunhui....@mediatek.com>
Reviewed-by: CK Hu <ck...@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 8 ++++++++
> drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 3db959fed493..df27107b1f0b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit {
>
> struct mtk_dpi_conf {
> const u32 reg_h_fre_con;
> + bool edge_sel_en;
> };
>
> static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
> @@ -350,6 +351,12 @@ static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
> mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
> }
>
> +static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
> +{
> + if (dpi->conf->edge_sel_en)
> + mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
> +}
> +
> static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
> enum mtk_dpi_out_color_format format)
> {
> @@ -535,6 +542,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> mtk_dpi_config_yc_map(dpi, dpi->yc_map);
> mtk_dpi_config_color_format(dpi, dpi->color_format);
> mtk_dpi_config_2n_h_fre(dpi);
> + mtk_dpi_config_disable_edge(dpi);
> mtk_dpi_sw_reset(dpi, false);
>
> return 0;
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index 040444d7718d..d9db8c4cacd7 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -223,5 +223,6 @@
> #define ESAV_CODE2 (0xFFF << 0)
> #define ESAV_CODE3_MSB BIT(16)
>
> +#define EDGE_SEL_EN BIT(5)
> #define H_FRE_2N BIT(25)
> #endif /* __MTK_DPI_REGS_H */
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