From: Jerome Glisse <jgli...@redhat.com>
Signed-off-by: Jerome Glisse <jgli...@redhat.com>
---
drivers/gpu/drm/radeon/radeon.h | 528 +++++++++++++++++-----------------
drivers/gpu/drm/radeon/radeon_ring.c | 3 +-
2 files changed, 267 insertions(+), 264 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 3fbb469..efc642a 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -132,9 +132,9 @@ extern int radeon_lockup_timeout;
* Errata workarounds.
*/
enum radeon_pll_errata {
- CHIP_ERRATA_R300_CG = 0x00000001,
- CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
- CHIP_ERRATA_PLL_DELAY = 0x00000004
+ CHIP_ERRATA_R300_CG = 0x00000001,
+ CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
+ CHIP_ERRATA_PLL_DELAY = 0x00000004
};
@@ -218,17 +218,17 @@ void radeon_dummy_page_fini(struct radeon_device *rdev);
* Clocks
*/
struct radeon_clock {
- struct radeon_pll p1pll;
- struct radeon_pll p2pll;
- struct radeon_pll dcpll;
- struct radeon_pll spll;
- struct radeon_pll mpll;
+ struct radeon_pll p1pll;
+ struct radeon_pll p2pll;
+ struct radeon_pll dcpll;
+ struct radeon_pll spll;
+ struct radeon_pll mpll;
/* 10 Khz units */
- uint32_t default_mclk;
- uint32_t default_sclk;
- uint32_t default_dispclk;
- uint32_t dp_extclk;
- uint32_t max_pixel_clock;
+ uint32_t default_mclk;
+ uint32_t default_sclk;
+ uint32_t default_dispclk;
+ uint32_t dp_extclk;
+ uint32_t max_pixel_clock;
};
/*
@@ -296,7 +296,7 @@ unsigned radeon_fence_count_emitted(struct radeon_device
*rdev, int ring);
* Tiling registers
*/
struct radeon_surface_reg {
- struct radeon_bo *bo;
+ struct radeon_bo *bo;
};
#define RADEON_GEM_MAX_SURFACES 8
@@ -305,7 +305,7 @@ struct radeon_surface_reg {
* TTM.
*/
struct radeon_mman {
- struct ttm_bo_global_ref bo_global_ref;
+ struct ttm_bo_global_ref bo_global_ref;
struct drm_global_reference mem_global_ref;
struct ttm_bo_device bdev;
bool mem_global_referenced;
@@ -351,12 +351,12 @@ struct radeon_bo {
#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
struct radeon_bo_list {
- struct ttm_validate_buffer tv;
- struct radeon_bo *bo;
- uint64_t gpu_offset;
- unsigned rdomain;
- unsigned wdomain;
- u32 tiling_flags;
+ struct ttm_validate_buffer tv;
+ struct radeon_bo *bo;
+ uint64_t gpu_offset;
+ unsigned rdomain;
+ unsigned wdomain;
+ u32 tiling_flags;
};
/* sub-allocation manager, it has to be protected by another lock.
@@ -522,7 +522,7 @@ struct radeon_mc {
int vram_mtrr;
bool vram_is_ddr;
bool igp_sideport_enabled;
- u64 gtt_base_align;
+ u64 gtt_base_align;
};
bool radeon_combios_sideport_present(struct radeon_device *rdev);
@@ -533,7 +533,7 @@ bool radeon_atombios_sideport_present(struct radeon_device
*rdev);
*/
struct radeon_scratch {
unsigned num_reg;
- uint32_t reg_base;
+ uint32_t reg_base;
bool free[32];
uint32_t reg[32];
};
@@ -547,55 +547,55 @@ void radeon_scratch_free(struct radeon_device *rdev,
uint32_t reg);
*/
struct radeon_unpin_work {
- struct work_struct work;
- struct radeon_device *rdev;
- int crtc_id;
- struct radeon_fence *fence;
- struct drm_pending_vblank_event *event;
- struct radeon_bo *old_rbo;
- u64 new_crtc_base;
+ struct work_struct work;
+ struct radeon_device *rdev;
+ int crtc_id;
+ struct radeon_fence *fence;
+ struct drm_pending_vblank_event *event;
+ struct radeon_bo *old_rbo;
+ u64 new_crtc_base;
};
struct r500_irq_stat_regs {
- u32 disp_int;
- u32 hdmi0_status;
+ u32 disp_int;
+ u32 hdmi0_status;
};
struct r600_irq_stat_regs {
- u32 disp_int;
- u32 disp_int_cont;
- u32 disp_int_cont2;
- u32 d1grph_int;
- u32 d2grph_int;
- u32 hdmi0_status;
- u32 hdmi1_status;
+ u32 disp_int;
+ u32 disp_int_cont;
+ u32 disp_int_cont2;
+ u32 d1grph_int;
+ u32 d2grph_int;
+ u32 hdmi0_status;
+ u32 hdmi1_status;
};
struct evergreen_irq_stat_regs {
- u32 disp_int;
- u32 disp_int_cont;
- u32 disp_int_cont2;
- u32 disp_int_cont3;
- u32 disp_int_cont4;
- u32 disp_int_cont5;
- u32 d1grph_int;
- u32 d2grph_int;
- u32 d3grph_int;
- u32 d4grph_int;
- u32 d5grph_int;
- u32 d6grph_int;
- u32 afmt_status1;
- u32 afmt_status2;
- u32 afmt_status3;
- u32 afmt_status4;
- u32 afmt_status5;
- u32 afmt_status6;
+ u32 disp_int;
+ u32 disp_int_cont;
+ u32 disp_int_cont2;
+ u32 disp_int_cont3;
+ u32 disp_int_cont4;
+ u32 disp_int_cont5;
+ u32 d1grph_int;
+ u32 d2grph_int;
+ u32 d3grph_int;
+ u32 d4grph_int;
+ u32 d5grph_int;
+ u32 d6grph_int;
+ u32 afmt_status1;
+ u32 afmt_status2;
+ u32 afmt_status3;
+ u32 afmt_status4;
+ u32 afmt_status5;
+ u32 afmt_status6;
};
union radeon_irq_stat_regs {
- struct r500_irq_stat_regs r500;
- struct r600_irq_stat_regs r600;
- struct evergreen_irq_stat_regs evergreen;
+ struct r500_irq_stat_regs r500;
+ struct r600_irq_stat_regs r600;
+ struct evergreen_irq_stat_regs evergreen;
};
#define RADEON_MAX_HPD_PINS 6
@@ -603,21 +603,21 @@ union radeon_irq_stat_regs {
#define RADEON_MAX_AFMT_BLOCKS 6
struct radeon_irq {
- bool installed;
- bool sw_int[RADEON_NUM_RINGS];
- bool crtc_vblank_int[RADEON_MAX_CRTCS];
- bool pflip[RADEON_MAX_CRTCS];
- wait_queue_head_t vblank_queue;
- bool hpd[RADEON_MAX_HPD_PINS];
- bool gui_idle;
- bool gui_idle_acked;
- wait_queue_head_t idle_queue;
- bool afmt[RADEON_MAX_AFMT_BLOCKS];
- spinlock_t sw_lock;
- int sw_refcount[RADEON_NUM_RINGS];
- union radeon_irq_stat_regs stat_regs;
- spinlock_t pflip_lock[RADEON_MAX_CRTCS];
- int pflip_refcount[RADEON_MAX_CRTCS];
+ bool installed;
+ bool sw_int[RADEON_NUM_RINGS];
+ bool crtc_vblank_int[RADEON_MAX_CRTCS];
+ bool pflip[RADEON_MAX_CRTCS];
+ wait_queue_head_t vblank_queue;
+ bool hpd[RADEON_MAX_HPD_PINS];
+ bool gui_idle;
+ bool gui_idle_acked;
+ wait_queue_head_t idle_queue;
+ bool afmt[RADEON_MAX_AFMT_BLOCKS];
+ spinlock_t sw_lock;
+ int sw_refcount[RADEON_NUM_RINGS];
+ union radeon_irq_stat_regs stat_regs;
+ spinlock_t pflip_lock[RADEON_MAX_CRTCS];
+ int pflip_refcount[RADEON_MAX_CRTCS];
};
int radeon_irq_kms_init(struct radeon_device *rdev);
@@ -730,8 +730,8 @@ struct r600_ih {
unsigned ring_size;
uint64_t gpu_addr;
uint32_t ptr_mask;
- spinlock_t lock;
- bool enabled;
+ spinlock_t lock;
+ bool enabled;
};
struct r600_blit_cp_primitives {
@@ -752,15 +752,15 @@ struct r600_blit_cp_primitives {
};
struct r600_blit {
- struct radeon_bo *shader_obj;
- struct r600_blit_cp_primitives primitives;
- int max_dim;
- int ring_size_common;
- int ring_size_per_loop;
- u64 shader_gpu_addr;
- u32 vs_offset, ps_offset;
- u32 state_offset;
- u32 state_len;
+ struct radeon_bo *shader_obj;
+ struct r600_blit_cp_primitives primitives;
+ int max_dim;
+ int ring_size_common;
+ int ring_size_per_loop;
+ u64 shader_gpu_addr;
+ u32 vs_offset, ps_offset;
+ u32 state_offset;
+ u32 state_len;
};
void r600_blit_suspend(struct radeon_device *rdev);
@@ -895,8 +895,8 @@ struct radeon_wb {
struct radeon_bo *wb_obj;
volatile uint32_t *wb;
uint64_t gpu_addr;
- bool enabled;
- bool use_event;
+ bool enabled;
+ bool use_event;
};
#define RADEON_WB_SCRATCH_OFFSET 0
@@ -996,19 +996,23 @@ enum radeon_int_thermal_type {
};
struct radeon_voltage {
- enum radeon_voltage_type type;
+ enum radeon_voltage_type type;
/* gpio voltage */
- struct radeon_gpio_rec gpio;
- u32 delay; /* delay in usec from voltage drop to sclk change */
- bool active_high; /* voltage drop is active when bit is high */
+ struct radeon_gpio_rec gpio;
+ /* delay in usec from voltage drop to sclk change */
+ u32 delay;
+ /* voltage drop is active when bit is high */
+ bool active_high;
/* VDDC voltage */
- u8 vddc_id; /* index into vddc voltage table */
- u8 vddci_id; /* index into vddci voltage table */
- bool vddci_enabled;
+ /* index into vddc voltage table */
+ u8 vddc_id;
+ /* index into vddci voltage table */
+ u8 vddci_id;
+ bool vddci_enabled;
/* r6xx+ sw */
- u16 voltage;
+ u16 voltage;
/* evergreen+ vddci */
- u16 vddci;
+ u16 vddci;
};
/* clock mode flags */
@@ -1016,29 +1020,29 @@ struct radeon_voltage {
struct radeon_pm_clock_info {
/* memory clock */
- u32 mclk;
+ u32 mclk;
/* engine clock */
- u32 sclk;
+ u32 sclk;
/* voltage info */
- struct radeon_voltage voltage;
+ struct radeon_voltage voltage;
/* standardized clock flags */
- u32 flags;
+ u32 flags;
};
/* state flags */
#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
struct radeon_power_state {
- enum radeon_pm_state_type type;
- struct radeon_pm_clock_info *clock_info;
+ enum radeon_pm_state_type type;
+ struct radeon_pm_clock_info *clock_info;
/* number of valid clock modes in this power state */
- int num_clock_modes;
- struct radeon_pm_clock_info *default_clock_mode;
+ int num_clock_modes;
+ struct radeon_pm_clock_info *default_clock_mode;
/* standardized state flags */
- u32 flags;
- u32 misc; /* vbios specific flags */
- u32 misc2; /* vbios specific flags */
- int pcie_lanes; /* pcie lanes */
+ u32 flags;
+ u32 misc; /* vbios specific flags */
+ u32 misc2; /* vbios specific flags */
+ int pcie_lanes; /* pcie lanes */
};
/*
@@ -1047,57 +1051,57 @@ struct radeon_power_state {
#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
struct radeon_pm {
- struct mutex mutex;
- u32 active_crtcs;
- int active_crtc_count;
- int req_vblank;
- bool vblank_sync;
- bool gui_idle;
- fixed20_12 max_bandwidth;
- fixed20_12 igp_sideport_mclk;
- fixed20_12 igp_system_mclk;
- fixed20_12 igp_ht_link_clk;
- fixed20_12 igp_ht_link_width;
- fixed20_12 k8_bandwidth;
- fixed20_12 sideport_bandwidth;
- fixed20_12 ht_bandwidth;
- fixed20_12 core_bandwidth;
- fixed20_12 sclk;
- fixed20_12 mclk;
- fixed20_12 needed_bandwidth;
- struct radeon_power_state *power_state;
+ struct mutex mutex;
+ u32 active_crtcs;
+ int active_crtc_count;
+ int req_vblank;
+ bool vblank_sync;
+ bool gui_idle;
+ fixed20_12 max_bandwidth;
+ fixed20_12 igp_sideport_mclk;
+ fixed20_12 igp_system_mclk;
+ fixed20_12 igp_ht_link_clk;
+ fixed20_12 igp_ht_link_width;
+ fixed20_12 k8_bandwidth;
+ fixed20_12 sideport_bandwidth;
+ fixed20_12 ht_bandwidth;
+ fixed20_12 core_bandwidth;
+ fixed20_12 sclk;
+ fixed20_12 mclk;
+ fixed20_12 needed_bandwidth;
+ struct radeon_power_state *power_state;
/* number of valid power states */
- int num_power_states;
- int current_power_state_index;
- int current_clock_mode_index;
- int requested_power_state_index;
- int requested_clock_mode_index;
- int default_power_state_index;
- u32 current_sclk;
- u32 current_mclk;
- u16 current_vddc;
- u16 current_vddci;
- u32 default_sclk;
- u32 default_mclk;
- u16 default_vddc;
- u16 default_vddci;
- struct radeon_i2c_chan *i2c_bus;
+ int num_power_states;
+ int current_power_state_index;
+ int current_clock_mode_index;
+ int requested_power_state_index;
+ int requested_clock_mode_index;
+ int default_power_state_index;
+ u32 current_sclk;
+ u32 current_mclk;
+ u16 current_vddc;
+ u16 current_vddci;
+ u32 default_sclk;
+ u32 default_mclk;
+ u16 default_vddc;
+ u16 default_vddci;
+ struct radeon_i2c_chan *i2c_bus;
/* selected pm method */
- enum radeon_pm_method pm_method;
+ enum radeon_pm_method pm_method;
/* dynpm power management */
- struct delayed_work dynpm_idle_work;
- enum radeon_dynpm_state dynpm_state;
+ struct delayed_work dynpm_idle_work;
+ enum radeon_dynpm_state dynpm_state;
enum radeon_dynpm_action dynpm_planned_action;
- unsigned long dynpm_action_timeout;
- bool dynpm_can_upclock;
- bool dynpm_can_downclock;
+ unsigned long dynpm_action_timeout;
+ bool dynpm_can_upclock;
+ bool dynpm_can_downclock;
/* profile-based power management */
- enum radeon_pm_profile_type profile;
- int profile_index;
- struct radeon_pm_profile profiles[PM_PROFILE_MAX];
+ enum radeon_pm_profile_type profile;
+ int profile_index;
+ struct radeon_pm_profile profiles[PM_PROFILE_MAX];
/* internal thermal controller on rv6xx+ */
- enum radeon_int_thermal_type int_thermal_type;
- struct device *int_hwmon_dev;
+ enum radeon_int_thermal_type int_thermal_type;
+ struct device *int_hwmon_dev;
};
int radeon_pm_get_type_index(struct radeon_device *rdev,
@@ -1320,97 +1324,97 @@ struct rv770_asic {
};
struct evergreen_asic {
- unsigned num_ses;
- unsigned max_pipes;
- unsigned max_tile_pipes;
- unsigned max_simds;
- unsigned max_backends;
- unsigned max_gprs;
- unsigned max_threads;
- unsigned max_stack_entries;
- unsigned max_hw_contexts;
- unsigned max_gs_threads;
- unsigned sx_max_export_size;
- unsigned sx_max_export_pos_size;
- unsigned sx_max_export_smx_size;
- unsigned sq_num_cf_insts;
- unsigned sx_num_of_sets;
- unsigned sc_prim_fifo_size;
- unsigned sc_hiz_tile_fifo_size;
- unsigned sc_earlyz_tile_fifo_size;
- unsigned tiling_nbanks;
- unsigned tiling_npipes;
- unsigned tiling_group_size;
- unsigned tile_config;
- unsigned backend_map;
+ unsigned num_ses;
+ unsigned max_pipes;
+ unsigned max_tile_pipes;
+ unsigned max_simds;
+ unsigned max_backends;
+ unsigned max_gprs;
+ unsigned max_threads;
+ unsigned max_stack_entries;
+ unsigned max_hw_contexts;
+ unsigned max_gs_threads;
+ unsigned sx_max_export_size;
+ unsigned sx_max_export_pos_size;
+ unsigned sx_max_export_smx_size;
+ unsigned sq_num_cf_insts;
+ unsigned sx_num_of_sets;
+ unsigned sc_prim_fifo_size;
+ unsigned sc_hiz_tile_fifo_size;
+ unsigned sc_earlyz_tile_fifo_size;
+ unsigned tiling_nbanks;
+ unsigned tiling_npipes;
+ unsigned tiling_group_size;
+ unsigned tile_config;
+ unsigned backend_map;
};
struct cayman_asic {
- unsigned max_shader_engines;
- unsigned max_pipes_per_simd;
- unsigned max_tile_pipes;
- unsigned max_simds_per_se;
- unsigned max_backends_per_se;
- unsigned max_texture_channel_caches;
- unsigned max_gprs;
- unsigned max_threads;
- unsigned max_gs_threads;
- unsigned max_stack_entries;
- unsigned sx_num_of_sets;
- unsigned sx_max_export_size;
- unsigned sx_max_export_pos_size;
- unsigned sx_max_export_smx_size;
- unsigned max_hw_contexts;
- unsigned sq_num_cf_insts;
- unsigned sc_prim_fifo_size;
- unsigned sc_hiz_tile_fifo_size;
- unsigned sc_earlyz_tile_fifo_size;
-
- unsigned num_shader_engines;
- unsigned num_shader_pipes_per_simd;
- unsigned num_tile_pipes;
- unsigned num_simds_per_se;
- unsigned num_backends_per_se;
- unsigned backend_disable_mask_per_asic;
- unsigned backend_map;
- unsigned num_texture_channel_caches;
- unsigned mem_max_burst_length_bytes;
- unsigned mem_row_size_in_kb;
- unsigned shader_engine_tile_size;
- unsigned num_gpus;
- unsigned multi_gpu_tile_size;
-
- unsigned tile_config;
+ unsigned max_shader_engines;
+ unsigned max_pipes_per_simd;
+ unsigned max_tile_pipes;
+ unsigned max_simds_per_se;
+ unsigned max_backends_per_se;
+ unsigned max_texture_channel_caches;
+ unsigned max_gprs;
+ unsigned max_threads;
+ unsigned max_gs_threads;
+ unsigned max_stack_entries;
+ unsigned sx_num_of_sets;
+ unsigned sx_max_export_size;
+ unsigned sx_max_export_pos_size;
+ unsigned sx_max_export_smx_size;
+ unsigned max_hw_contexts;
+ unsigned sq_num_cf_insts;
+ unsigned sc_prim_fifo_size;
+ unsigned sc_hiz_tile_fifo_size;
+ unsigned sc_earlyz_tile_fifo_size;
+
+ unsigned num_shader_engines;
+ unsigned num_shader_pipes_per_simd;
+ unsigned num_tile_pipes;
+ unsigned num_simds_per_se;
+ unsigned num_backends_per_se;
+ unsigned backend_disable_mask_per_asic;
+ unsigned backend_map;
+ unsigned num_texture_channel_caches;
+ unsigned mem_max_burst_length_bytes;
+ unsigned mem_row_size_in_kb;
+ unsigned shader_engine_tile_size;
+ unsigned num_gpus;
+ unsigned multi_gpu_tile_size;
+
+ unsigned tile_config;
};
struct si_asic {
- unsigned max_shader_engines;
- unsigned max_pipes_per_simd;
- unsigned max_tile_pipes;
- unsigned max_simds_per_se;
- unsigned max_backends_per_se;
- unsigned max_texture_channel_caches;
- unsigned max_gprs;
- unsigned max_gs_threads;
- unsigned max_hw_contexts;
- unsigned sc_prim_fifo_size_frontend;
- unsigned sc_prim_fifo_size_backend;
- unsigned sc_hiz_tile_fifo_size;
- unsigned sc_earlyz_tile_fifo_size;
-
- unsigned num_shader_engines;
- unsigned num_tile_pipes;
- unsigned num_backends_per_se;
- unsigned backend_disable_mask_per_asic;
- unsigned backend_map;
- unsigned num_texture_channel_caches;
- unsigned mem_max_burst_length_bytes;
- unsigned mem_row_size_in_kb;
- unsigned shader_engine_tile_size;
- unsigned num_gpus;
- unsigned multi_gpu_tile_size;
-
- unsigned tile_config;
+ unsigned max_shader_engines;
+ unsigned max_pipes_per_simd;
+ unsigned max_tile_pipes;
+ unsigned max_simds_per_se;
+ unsigned max_backends_per_se;
+ unsigned max_texture_channel_caches;
+ unsigned max_gprs;
+ unsigned max_gs_threads;
+ unsigned max_hw_contexts;
+ unsigned sc_prim_fifo_size_frontend;
+ unsigned sc_prim_fifo_size_backend;
+ unsigned sc_hiz_tile_fifo_size;
+ unsigned sc_earlyz_tile_fifo_size;
+
+ unsigned num_shader_engines;
+ unsigned num_tile_pipes;
+ unsigned num_backends_per_se;
+ unsigned backend_disable_mask_per_asic;
+ unsigned backend_map;
+ unsigned num_texture_channel_caches;
+ unsigned mem_max_burst_length_bytes;
+ unsigned mem_row_size_in_kb;
+ unsigned shader_engine_tile_size;
+ unsigned num_gpus;
+ unsigned multi_gpu_tile_size;
+
+ unsigned tile_config;
};
union radeon_asic_config {
@@ -1531,32 +1535,32 @@ struct radeon_device {
bool suspend;
bool need_dma32;
bool accel_working;
- struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
- const struct firmware *me_fw; /* all family ME firmware */
- const struct firmware *pfp_fw; /* r6/700 PFP firmware */
- const struct firmware *rlc_fw; /* r6/700 RLC firmware */
- const struct firmware *mc_fw; /* NI MC firmware */
- const struct firmware *ce_fw; /* SI CE firmware */
- struct r600_blit r600_blit;
- struct r600_vram_scratch vram_scratch;
- int msi_enabled; /* msi enabled */
- struct r600_ih ih; /* r6/700 interrupt ring */
- struct si_rlc rlc;
- struct work_struct hotplug_work;
- struct work_struct audio_work;
- int num_crtc; /* number of crtcs */
- struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
- struct mutex vram_mutex;
- struct r600_audio audio; /* audio stuff */
- struct notifier_block acpi_nb;
+ struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
+ const struct firmware *me_fw; /* all family ME firmware */
+ const struct firmware *pfp_fw; /* r6/700 PFP firmware
*/
+ const struct firmware *rlc_fw; /* r6/700 RLC firmware
*/
+ const struct firmware *mc_fw; /* NI MC firmware */
+ const struct firmware *ce_fw; /* SI CE firmware */
+ struct r600_blit r600_blit;
+ struct r600_vram_scratch vram_scratch;
+ int msi_enabled; /* msi enabled */
+ struct r600_ih ih; /* r6/700 interrupt ring */
+ struct si_rlc rlc;
+ struct work_struct hotplug_work;
+ struct work_struct audio_work;
+ int num_crtc; /* number of crtcs */
+ struct mutex dc_hw_i2c_mutex; /* display controller
hw i2c mutex */
+ struct mutex vram_mutex;
+ struct r600_audio audio; /* audio stuff */
+ struct notifier_block acpi_nb;
/* only one userspace can use Hyperz features or CMASK at a time */
- struct drm_file *hyperz_filp;
- struct drm_file *cmask_filp;
+ struct drm_file *hyperz_filp;
+ struct drm_file *cmask_filp;
/* i2c buses */
- struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
+ struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
/* debugfs */
- struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
- unsigned debugfs_count;
+ struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
+ unsigned debugfs_count;
/* virtual memory */
struct radeon_vm_manager vm_manager;
/* lockup blob dumping */
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c
b/drivers/gpu/drm/radeon/radeon_ring.c
index 6982d8f..9f8d9d7 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -494,7 +494,6 @@ static int radeon_debugfs_sa_info(struct seq_file *m, void
*data)
radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
return 0;
-
}
static int radeon_debugfs_lockup(struct seq_file *m, void *data)
@@ -504,7 +503,7 @@ static int radeon_debugfs_lockup(struct seq_file *m, void
*data)
}
static struct drm_info_list radeon_debugfs_sa_list[] = {
- {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
+ {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
};
static struct drm_info_list radeon_debugfs_lockup_list[] = {
--
1.7.7.6
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