From: Quentin Schulz <quentin.sch...@free-electrons.com>
In DP 1.4, interval between link status and adjust request read for the
clock recovery phase is fixed to 100us whatever the value of the
register is.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
Signed-off-by: Damian Kos <d...@cadence.com>
---
drivers/gpu/drm/drm_dp_helper.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index b6a27ab..92f3880 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -152,6 +152,11 @@ void drm_dp_link_train_clock_recovery_delay(const u8
dpcd[DP_RECEIVER_CAP_SIZE])
unsigned int training_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
DP_TRAINING_AUX_RD_INTERVAL_MASK;
+ if (dpcd[DP_DPCD_REV] == 0x14) {
+ udelay(100);
+ return;
+ }
+
if (training_interval == 0)
udelay(100);
else
--
1.7.1
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