On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec <jernej.skra...@siol.net> wrote: > Some DW HDMI PHYs, like those found in A64 and R40 SoCs, can select > between two clock parents. > > Add code which reads second PLL from DT. > > Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
This patch by itself does not do anything. It should be merged with the next one. _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
