[PATCH 08/13] drm/kms/mode/pl111-display: using helper function drm_display_mode_to_videomode for calculating timing parameters

[Satendra Singh Thakur]

To avoid duplicate logic for the same

Signed-off-by: Satendra Singh Thakur <satendr...@samsung.com>
Cc: Madhur Verma <madhur.ve...@samsung.com>
Cc: Hemanshu Srivastava <hemansh...@samsung.com>
---
 drivers/gpu/drm/pl111/pl111_display.c | 40 +++++++++++++----------------------
 1 file changed, 15 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/pl111/pl111_display.c 
b/drivers/gpu/drm/pl111/pl111_display.c
index 3106464..104f318 100644
--- a/drivers/gpu/drm/pl111/pl111_display.c
+++ b/drivers/gpu/drm/pl111/pl111_display.c
@@ -24,6 +24,7 @@
 #include <drm/drm_gem_cma_helper.h>
 #include <drm/drm_gem_framebuffer_helper.h>
 #include <drm/drm_fb_cma_helper.h>
+#include <video/videomode.h>
 
 #include "pl111_drm.h"
 
@@ -130,13 +131,14 @@ static void pl111_display_enable(struct 
drm_simple_display_pipe *pipe,
        struct drm_framebuffer *fb = plane->state->fb;
        struct drm_connector *connector = priv->connector;
        struct drm_bridge *bridge = priv->bridge;
+       struct videomode vm;
        u32 cntl;
-       u32 ppl, hsw, hfp, hbp;
-       u32 lpp, vsw, vfp, vbp;
-       u32 cpl, tim2;
+       u32 tim2;
        int ret;
 
-       ret = clk_set_rate(priv->clk, mode->clock * 1000);
+       drm_display_mode_to_videomode(mode, &vm);
+
+       ret = clk_set_rate(priv->clk, vm.pixelclock);
        if (ret) {
                dev_err(drm->dev,
                        "Failed to set pixel clock rate to %d: %d\n",
@@ -145,27 +147,15 @@ static void pl111_display_enable(struct 
drm_simple_display_pipe *pipe,
 
        clk_prepare_enable(priv->clk);
 
-       ppl = (mode->hdisplay / 16) - 1;
-       hsw = mode->hsync_end - mode->hsync_start - 1;
-       hfp = mode->hsync_start - mode->hdisplay - 1;
-       hbp = mode->htotal - mode->hsync_end - 1;
-
-       lpp = mode->vdisplay - 1;
-       vsw = mode->vsync_end - mode->vsync_start - 1;
-       vfp = mode->vsync_start - mode->vdisplay;
-       vbp = mode->vtotal - mode->vsync_end;
-
-       cpl = mode->hdisplay - 1;
-
-       writel((ppl << 2) |
-              (hsw << 8) |
-              (hfp << 16) |
-              (hbp << 24),
+       writel((((vm.hactive >> 4) - 1) << 2) |
+              ((vm.hsync_len - 1) << 8) |
+              ((vm.hfront_porch - 1) << 16) |
+              ((vm.hback_porch - 1) << 24),
               priv->regs + CLCD_TIM0);
-       writel(lpp |
-              (vsw << 10) |
-              (vfp << 16) |
-              (vbp << 24),
+       writel((vm.vactive - 1) |
+              ((vm.vsync_len - 1) << 10) |
+              ((vm.vfront_porch) << 16) |
+              ((vm.vback_porch) << 24),
               priv->regs + CLCD_TIM1);
 
        spin_lock(&priv->tim2_lock);
@@ -214,7 +204,7 @@ static void pl111_display_enable(struct 
drm_simple_display_pipe *pipe,
                        tim2 ^= TIM2_IPC;
        }
 
-       tim2 |= cpl << 16;
+       tim2 |= (vm.hactive - 1) << 16;
        writel(tim2, priv->regs + CLCD_TIM2);
        spin_unlock(&priv->tim2_lock);
 
-- 
2.7.4

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