tree: git://people.freedesktop.org/~agd5f/linux.git drm-next-4.17-wip
head: 1d0e528594e2040c6c208be32bad4ad57437aabb
commit: 1d0e528594e2040c6c208be32bad4ad57437aabb [390/390] drm/amdgpu: used
cached pcie gen info for SI
config: powerpc64-allyesconfig (attached as .config)
compiler: powerpc64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 1d0e528594e2040c6c208be32bad4ad57437aabb
# save the attached .config to linux build tree
make.cross ARCH=powerpc64
All errors (new ones prefixed by >>):
drivers/gpu//drm/amd/amdgpu/si_dpm.c: In function 'si_dpm_init':
>> drivers/gpu//drm/amd/amdgpu/si_dpm.c:7317:29: error:
>> 'CAIL_PCIE_LINK_SPEED_SUPPORT_MASK' undeclared (first use in this function);
>> did you mean 'LC_TARGET_LINK_SPEED_OVERRIDE_MASK'?
(adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LC_TARGET_LINK_SPEED_OVERRIDE_MASK
drivers/gpu//drm/amd/amdgpu/si_dpm.c:7317:29: note: each undeclared
identifier is reported only once for each function it appears in
drivers/gpu//drm/amd/amdgpu/si_dpm.c:7318:3: error:
'CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT' undeclared (first use in this function);
did you mean 'CAIL_PCIE_LINK_SPEED_SUPPORT_MASK'?
CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CAIL_PCIE_LINK_SPEED_SUPPORT_MASK
vim +7317 drivers/gpu//drm/amd/amdgpu/si_dpm.c
7298
7299 static int si_dpm_init(struct amdgpu_device *adev)
7300 {
7301 struct rv7xx_power_info *pi;
7302 struct evergreen_power_info *eg_pi;
7303 struct ni_power_info *ni_pi;
7304 struct si_power_info *si_pi;
7305 struct atom_clock_dividers dividers;
7306 int ret;
7307
7308 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7309 if (si_pi == NULL)
7310 return -ENOMEM;
7311 adev->pm.dpm.priv = si_pi;
7312 ni_pi = &si_pi->ni;
7313 eg_pi = &ni_pi->eg;
7314 pi = &eg_pi->rv7xx;
7315
7316 si_pi->sys_pcie_mask =
> 7317 (adev->pm.pcie_gen_mask &
> CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
7318 CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
7319 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7320 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7321
7322 si_set_max_cu_value(adev);
7323
7324 rv770_get_max_vddc(adev);
7325 si_get_leakage_vddc(adev);
7326 si_patch_dependency_tables_based_on_leakage(adev);
7327
7328 pi->acpi_vddc = 0;
7329 eg_pi->acpi_vddci = 0;
7330 pi->min_vddc_in_table = 0;
7331 pi->max_vddc_in_table = 0;
7332
7333 ret = amdgpu_get_platform_caps(adev);
7334 if (ret)
7335 return ret;
7336
7337 ret = amdgpu_parse_extended_power_table(adev);
7338 if (ret)
7339 return ret;
7340
7341 ret = si_parse_power_table(adev);
7342 if (ret)
7343 return ret;
7344
7345 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7346 kzalloc(4 * sizeof(struct
amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7347 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries)
{
7348 amdgpu_free_extended_power_table(adev);
7349 return -ENOMEM;
7350 }
7351 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7352
adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7353 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v
= 0;
7354
adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7355 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v
= 720;
7356
adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7357 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v
= 810;
7358
adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7359 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v
= 900;
7360
7361 if (adev->pm.dpm.voltage_response_time == 0)
7362 adev->pm.dpm.voltage_response_time =
R600_VOLTAGERESPONSETIME_DFLT;
7363 if (adev->pm.dpm.backbias_response_time == 0)
7364 adev->pm.dpm.backbias_response_time =
R600_BACKBIASRESPONSETIME_DFLT;
7365
7366 ret = amdgpu_atombios_get_clock_dividers(adev,
COMPUTE_ENGINE_PLL_PARAM,
7367 0, false, ÷rs);
7368 if (ret)
7369 pi->ref_div = dividers.ref_div + 1;
7370 else
7371 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7372
7373 eg_pi->smu_uvd_hs = false;
7374
7375 pi->mclk_strobe_mode_threshold = 40000;
7376 if (si_is_special_1gb_platform(adev))
7377 pi->mclk_stutter_mode_threshold = 0;
7378 else
7379 pi->mclk_stutter_mode_threshold =
pi->mclk_strobe_mode_threshold;
7380 pi->mclk_edc_enable_threshold = 40000;
7381 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7382
7383 ni_pi->mclk_rtt_mode_threshold =
eg_pi->mclk_edc_wr_enable_threshold;
7384
7385 pi->voltage_control =
7386 amdgpu_atombios_is_voltage_gpio(adev,
SET_VOLTAGE_TYPE_ASIC_VDDC,
7387 VOLTAGE_OBJ_GPIO_LUT);
7388 if (!pi->voltage_control) {
7389 si_pi->voltage_control_svi2 =
7390 amdgpu_atombios_is_voltage_gpio(adev,
SET_VOLTAGE_TYPE_ASIC_VDDC,
7391 VOLTAGE_OBJ_SVID2);
7392 if (si_pi->voltage_control_svi2)
7393 amdgpu_atombios_get_svi2_info(adev,
SET_VOLTAGE_TYPE_ASIC_VDDC,
7394 &si_pi->svd_gpio_id,
&si_pi->svc_gpio_id);
7395 }
7396
7397 pi->mvdd_control =
7398 amdgpu_atombios_is_voltage_gpio(adev,
SET_VOLTAGE_TYPE_ASIC_MVDDC,
7399 VOLTAGE_OBJ_GPIO_LUT);
7400
7401 eg_pi->vddci_control =
7402 amdgpu_atombios_is_voltage_gpio(adev,
SET_VOLTAGE_TYPE_ASIC_VDDCI,
7403 VOLTAGE_OBJ_GPIO_LUT);
7404 if (!eg_pi->vddci_control)
7405 si_pi->vddci_control_svi2 =
7406 amdgpu_atombios_is_voltage_gpio(adev,
SET_VOLTAGE_TYPE_ASIC_VDDCI,
7407 VOLTAGE_OBJ_SVID2);
7408
7409 si_pi->vddc_phase_shed_control =
7410 amdgpu_atombios_is_voltage_gpio(adev,
SET_VOLTAGE_TYPE_ASIC_VDDC,
7411 VOLTAGE_OBJ_PHASE_LUT);
7412
7413 rv770_get_engine_memory_ss(adev);
7414
7415 pi->asi = RV770_ASI_DFLT;
7416 pi->pasi = CYPRESS_HASI_DFLT;
7417 pi->vrc = SISLANDS_VRC_DFLT;
7418
7419 pi->gfx_clock_gating = true;
7420
7421 eg_pi->sclk_deep_sleep = true;
7422 si_pi->sclk_deep_sleep_above_low = false;
7423
7424 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7425 pi->thermal_protection = true;
7426 else
7427 pi->thermal_protection = false;
7428
7429 eg_pi->dynamic_ac_timing = true;
7430
7431 eg_pi->light_sleep = true;
7432 #if defined(CONFIG_ACPI)
7433 eg_pi->pcie_performance_request =
7434 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7435 #else
7436 eg_pi->pcie_performance_request = false;
7437 #endif
7438
7439 si_pi->sram_end = SMC_RAM_END;
7440
7441 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7442 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7443 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7444 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7445 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7446 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7447 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7448
7449 si_initialize_powertune_defaults(adev);
7450
7451 /* make sure dc limits are valid */
7452 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0)
||
7453 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7454 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7455 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7456
7457 si_pi->fan_ctrl_is_in_default_mode = true;
7458
7459 return 0;
7460 }
7461
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
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