This patch adds YUV2YUV registers to enable and control per-plane
RGB2RGB colos space conversion matrix.
Change-Id: I8f421222da3587caea6373e2201e918f0c5e2646
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 7 +++
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 48 +++++++++++++++++++++
2 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index aa8a5d2690376..fea5a087f4749 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -80,6 +80,13 @@ struct vop_misc {
};
struct vop_yuv2yuv {
+ struct vop_reg win0_r2r_en;
+ struct vop_reg win0_r2r_coefficients[12];
+ struct vop_reg win1_r2r_en;
+ struct vop_reg win1_r2r_coefficients[12];
+ struct vop_reg win2_r2r_en;
+ struct vop_reg win2_r2r_coefficients[12];
+
struct vop_reg win0_y2r_en;
struct vop_reg win0_y2r_coefficients[12];
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 0af95947f22d4..fb7b07aa4fa27 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -423,6 +423,54 @@ static const struct vop_output rk3399_output = {
};
static const struct vop_yuv2yuv rk3399_vop_yuv2yuv = {
+ .win0_r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0),
+ .win0_r2r_coefficients = {
+ VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 0, 0xffff, 0),
+ VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 0, 0xffff, 16),
+ VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 4, 0xffff, 0),
+ VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 4, 0xffff, 16),
+ VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 8, 0xffff, 0),
+ VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 8, 0xffff, 16),
+ VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 12, 0xffff, 0),
+ VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 12, 0xffff, 16),
+ VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 16, 0xffff, 0),
+ VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 20, 0xffffffff, 0),
+ VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 24, 0xffffffff, 0),
+ VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 28, 0xffffffff, 0),
+ },
+
+ .win1_r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 8),
+ .win1_r2r_coefficients = {
+ VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 0, 0xffff, 0),
+ VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 0, 0xffff, 16),
+ VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 4, 0xffff, 0),
+ VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 4, 0xffff, 16),
+ VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 8, 0xffff, 0),
+ VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 8, 0xffff, 16),
+ VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 12, 0xffff, 0),
+ VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 12, 0xffff, 16),
+ VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 16, 0xffff, 0),
+ VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 20, 0xffffffff, 0),
+ VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 24, 0xffffffff, 0),
+ VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 28, 0xffffffff, 0),
+ },
+
+ .win2_r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 16),
+ .win2_r2r_coefficients = {
+ VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 0, 0xffff, 0),
+ VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 0, 0xffff, 16),
+ VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 4, 0xffff, 0),
+ VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 4, 0xffff, 16),
+ VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 8, 0xffff, 0),
+ VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 8, 0xffff, 16),
+ VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 12, 0xffff, 0),
+ VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 12, 0xffff, 16),
+ VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 16, 0xffff, 0),
+ VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 20, 0xffffffff, 0),
+ VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 24, 0xffffffff, 0),
+ VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 28, 0xffffffff, 0),
+ },
+
.win0_y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1),
.win0_y2r_coefficients = {
VOP_REG(RK3399_WIN1_YUV2YUV_Y2R + 0, 0xffff, 0),
--
2.16.1.291.g4437f3f132-goog
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