On Fri, 22 Dec 2017, Anusha Srivatsa <anusha.sriva...@intel.com> wrote:
> Forward Error Correction is supported on DP 1.4.
> This patch adds corresponding DPCD register definitions.
>
> v2: Add dri-devel mailing list to the CC list(Jani)
>
> v3: Change names, add missing masks (Manasi)
>
> v4: Add missing shifts to mask (Manasi)
>
> Cc: dri-devel@lists.freedesktop.org
> Cc: Ville Syrjala <ville.syrj...@linux.intel.com>
> Cc: Jani Nikula <jani.nik...@linux.intel.com>
> Cc: Manasi Navare <manasi.d.nav...@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
> Reviewed-by: Manasi Navare <manasi.d.nav...@intel.com>

Anusha, when a patch obviously falls between the cracks, like here,
please ping or resend it. Sure, the maintainers/committers should take
care of it, but when that doesn't happen, please follow through with
your work.

I was going to merge this now but I'm afraid I noticed that the
definitions are out of place. Everything else is in increasing DPCD
address order, these aren't.

Please fix that.

BR,
Jani.


> ---
>  include/drm/drm_dp_helper.h | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index da58a42..592e371 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -284,6 +284,36 @@
>  # define DP_DSC_BITS_PER_PIXEL_1_2          0x3
>  # define DP_DSC_BITS_PER_PIXEL_1            0x4
>  
> +/* DP Forward error Correction Registers */
> +#define DP_FEC_CAPABILITY                0x090
> +# define DP_FEC_CAPABLE                          (1 << 0)
> +# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP  (1 << 1)
> +# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP    (1 << 2)
> +# define DP_FEC_BIT_ERROR_COUNT_CAP      (1 << 3)
> +
> +#define DP_FEC_CONFIGURATION             0x120
> +# define DP_FEC_READY                            (1 << 0)
> +# define DP_FEC_ERR_COUNT_DIS                    (0 << 1)
> +# define DP_FEC_UNCORR_BLK_ERROR_COUNT           (1 << 1)
> +# define DP_FEC_CORR_BLK_ERROR_COUNT     (2 << 1)
> +# define DP_FEC_BIT_ERROR_COUNT                  (3 << 1)
> +# define DP_FEC_ERR_COUNT_SEL_MASK       (0xff << 4)
> +# define DP_FEC_LANE_0_SELECT                    (0 << 4)
> +# define DP_FEC_LANE_1_SELECT                    (1 << 4)
> +# define DP_FEC_LANE_2_SELECT                    (2 << 4)
> +# define DP_FEC_LANE_3_SELECT                    (3 << 4)
> +
> +#define DP_FEC_STATUS                            0x280
> +# define DP_FEC_DECODE_EN_DETECTED       (1 << 0)
> +# define DP_FEC_DECODE_DIS_DETECTED      (1 << 1)
> +
> +#define DP_FEC_ERROR_COUNT_LSB                   0x0281
> +
> +#define DP_FEC_ERROR_COUNT_MSB                   0x0282
> +# define DP_FEC_ERROR_COUNT_MASK         0x7F
> +# define DP_FEC_ERR_COUNT_SHIFT                  8
> +# define DP_FEC_ERR_COUNT_VALID                  (1 << 7)
> +
>  #define DP_PSR_SUPPORT                      0x070   /* XXX 1.2? */
>  # define DP_PSR_IS_SUPPORTED                1
>  # define DP_PSR2_IS_SUPPORTED                    2       /* eDP 1.4 */

-- 
Jani Nikula, Intel Open Source Technology Center
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