On Fri, Jan 26, 2018 at 02:16:56PM +0100, Thierry Escande wrote:
> From: zain wang <w...@rock-chips.com>
> 
> It's too early to detect fast link training, if other step after it
> failed, we will set fast_link flag to 1, and retry set_bridge again. In
> this case we will power down and power up panel power supply, and we
> will do fast link training since we have set fast_link flag to 1. In
> fact, we should do full link training now, not the fast link training.
> So we should move the fast link detection at the end of set_bridge.
> 
> Cc: Tomasz Figa <tf...@chromium.org>
> Signed-off-by: zain wang <w...@rock-chips.com>
> Signed-off-by: Douglas Anderson <diand...@chromium.org>
> Signed-off-by: Sean Paul <seanp...@chromium.org>
> Signed-off-by: Thierry Escande <thierry.esca...@collabora.com>
> Reviewed-by: Andrzej Hajda <a.ha...@samsung.com>
> ---
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 42 
> +++++++++++++---------
>  1 file changed, 26 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 
> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index e7ab871e62b5..bee0f7aa5c23 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -599,7 +599,7 @@ static int analogix_dp_process_equalizer_training(struct 
> analogix_dp_device *dp)
>  {
>       int lane, lane_count, retval;
>       u32 reg;
> -     u8 link_align, link_status[2], adjust_request[2], spread;
> +     u8 link_align, link_status[2], adjust_request[2];
>  
>       usleep_range(400, 401);
>  
> @@ -643,20 +643,6 @@ static int analogix_dp_process_equalizer_training(struct 
> analogix_dp_device *dp)
>               dev_dbg(dp->dev, "final lane count = %.2x\n",
>                       dp->link_train.lane_count);
>  
> -             retval = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD,
> -                                        &spread);
> -             if (retval != 1) {
> -                     dev_err(dp->dev, "failed to read downspread %d\n",
> -                             retval);
> -                     dp->fast_train_enable = false;
> -             } else {
> -                     dp->fast_train_enable =
> -                             (spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING) ?
> -                                     true : false;
> -             }
> -             dev_dbg(dp->dev, "fast link training %s\n",
> -                     dp->fast_train_enable ? "supported" : "unsupported");
> -
>               dp->link_train.lt_state = FINISHED;
>  
>               return 0;
> @@ -997,6 +983,22 @@ static irqreturn_t analogix_dp_irq_thread(int irq, void 
> *arg)
>       return IRQ_HANDLED;
>  }
>  
> +static int analogix_dp_fast_link_train_detection(struct analogix_dp_device 
> *dp)
> +{
> +     int ret;
> +     u8 spread;
> +
> +     ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
> +     if (ret != 1) {
> +             dev_err(dp->dev, "failed to read downspread %d\n", ret);
> +             return ret;
> +     }
> +     dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
> +     dev_dbg(dp->dev, "fast link training %s\n",
> +             dp->fast_train_enable ? "supported" : "unsupported");
> +     return 0;
> +}
> +
>  static int analogix_dp_commit(struct analogix_dp_device *dp)
>  {
>       int ret;
> @@ -1039,8 +1041,16 @@ static int analogix_dp_commit(struct 
> analogix_dp_device *dp)
>       if (ret)
>               return ret;
>  
> -     if (dp->psr_enable)
> +     if (dp->psr_enable) {
>               ret = analogix_dp_enable_sink_psr(dp);
> +             if (ret)
> +                     return ret;
> +     }
> +
> +     /* Check whether panel supports fast training */
> +     ret =  analogix_dp_fast_link_train_detection(dp);
> +     if (ret)
> +             dp->psr_enable = false;

You could probably flip this with psr_enable and just return on error instead of
flipping psr_enable back. Not a big deal either way.

Sean

>  
>       return ret;
>  }
> -- 
> 2.14.1
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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