Hi Sergei,
On Thursday, 21 December 2017 22:23:30 EET Sergei Shtylyov wrote:
> The LVDCR1 register for the R-Car gen3 SoCs was documented as having the
> layout different from the gen2 SoCs in the early R-Car gen3 manuals but
> since v0.52 the LVDCR1 layout is described as being the same as on the gen2
> SoCs; the old CHn control values are said to be prohibited now (and there
> seems to be no valid output signal when they are used).
>
> Fixes: 6bc2e15cf21c ("drm: rcar-du: lvds: Add R-Car Gen3 support")
> Signed-off-by: Sergei Shtylyov <sergei.shtyl...@cogentembedded.com>
I've tested this on Salvator-X H3 ES1.1, Salvator-XS H3 ES2.0 and Salvator-X
M3-W, and the LVDS output works correctly. I assume both settings work on
these SoCs, while only the new settings work on V3M. Thus,
Reviewed-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
and applied to my tree.
> ---
> drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 10 ++++------
> drivers/gpu/drm/rcar-du/rcar_lvds_regs.h | 6 ++----
> 2 files changed, 6 insertions(+), 10 deletions(-)
>
> Index: linux/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
> ===================================================================
> --- linux.orig/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
> +++ linux/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
> @@ -70,9 +70,8 @@ static void rcar_du_lvdsenc_start_gen2(s
>
> /* Turn all the channels on. */
> rcar_lvds_write(lvds, LVDCR1,
> - LVDCR1_CHSTBY_GEN2(3) | LVDCR1_CHSTBY_GEN2(2) |
> - LVDCR1_CHSTBY_GEN2(1) | LVDCR1_CHSTBY_GEN2(0) |
> - LVDCR1_CLKSTBY_GEN2);
> + LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
> + LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
>
> /*
> * Turn the PLL on, wait for the startup delay, and turn the output
> @@ -109,9 +108,8 @@ static void rcar_du_lvdsenc_start_gen3(s
>
> /* Turn all the channels on. */
> rcar_lvds_write(lvds, LVDCR1,
> - LVDCR1_CHSTBY_GEN3(3) | LVDCR1_CHSTBY_GEN3(2) |
> - LVDCR1_CHSTBY_GEN3(1) | LVDCR1_CHSTBY_GEN3(0) |
> - LVDCR1_CLKSTBY_GEN3);
> + LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
> + LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
>
> /*
> * Turn the PLL on, set it to LVDS normal mode, wait for the startup
> Index: linux/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h
> ===================================================================
> --- linux.orig/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h
> +++ linux/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h
> @@ -26,10 +26,8 @@
>
> #define LVDCR1 0x0004
> #define LVDCR1_CKSEL (1 << 15) /* Gen2 only */
> -#define LVDCR1_CHSTBY_GEN2(n) (3 << (2 + (n) * 2)) /* Gen2
> only */
> -#define LVDCR1_CHSTBY_GEN3(n) (1 << (2 + (n) * 2)) /* Gen3
> only */
> -#define LVDCR1_CLKSTBY_GEN2 (3 << 0) /* Gen2 only */
> -#define LVDCR1_CLKSTBY_GEN3 (1 << 0) /* Gen3 only */
> +#define LVDCR1_CHSTBY(n) (3 << (2 + (n) * 2))
> +#define LVDCR1_CLKSTBY (3 << 0)
>
> #define LVDPLLCR 0x0008
> #define LVDPLLCR_CEEN (1 << 14)
>
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--
Regards,
Laurent Pinchart
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