If the sink device is in HDMI mode, enable infoframe interrupt in scdt
irq handle function else call start_video function immediately, because
in DVI mode, there is no infoframe interrupt provided.
Rename start_hdmi function to start_video and get rid of the old
start_video function. In start_video, if the sink is DVI and mode is
MHL1 or MHl2, write appropriate values to registers else the path
should remain the same as in HDMI mode.
Signed-off-by: Maciej Purski <m.pur...@samsung.com>
---
drivers/gpu/drm/bridge/sil-sii8620.c | 37 ++++++++++++++++++------------------
drivers/gpu/drm/bridge/sil-sii8620.h | 2 ++
2 files changed, 21 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c
b/drivers/gpu/drm/bridge/sil-sii8620.c
index b7eb704..657a453 100644
--- a/drivers/gpu/drm/bridge/sil-sii8620.c
+++ b/drivers/gpu/drm/bridge/sil-sii8620.c
@@ -1169,8 +1169,19 @@ static void sii8620_set_infoframes(struct sii8620 *ctx)
sii8620_write_buf(ctx, REG_TPI_INFO_B0, buf, ret);
}
-static void sii8620_start_hdmi(struct sii8620 *ctx)
+static void sii8620_start_video(struct sii8620 *ctx)
{
+ if (!sii8620_is_mhl3(ctx))
+ sii8620_stop_video(ctx);
+
+ if (ctx->sink_type == SINK_DVI && !sii8620_is_mhl3(ctx)) {
+ sii8620_write(ctx, REG_RX_HDMI_CTRL2,
+ VAL_RX_HDMI_CTRL2_DEFVAL_DVI);
+ sii8620_write(ctx, REG_TPI_SC,
+ BIT_TPI_SC_TPI_OUTPUT_MODE_0_DVI);
+ return;
+ }
+
sii8620_write_seq_static(ctx,
REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL
| BIT_RX_HDMI_CTRL2_USE_AV_MUTE,
@@ -1229,21 +1240,6 @@ static void sii8620_start_hdmi(struct sii8620 *ctx)
sii8620_set_infoframes(ctx);
}
-static void sii8620_start_video(struct sii8620 *ctx)
-{
- if (!sii8620_is_mhl3(ctx))
- sii8620_stop_video(ctx);
-
- switch (ctx->sink_type) {
- case SINK_HDMI:
- sii8620_start_hdmi(ctx);
- break;
- case SINK_DVI:
- default:
- break;
- }
-}
-
static void sii8620_disable_hpd(struct sii8620 *ctx)
{
sii8620_setbits(ctx, REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID, 0);
@@ -1945,8 +1941,13 @@ static void sii8620_irq_scdt(struct sii8620 *ctx)
if (stat & BIT_INTR_SCDT_CHANGE) {
u8 cstat = sii8620_readb(ctx, REG_TMDS_CSTAT_P3);
- if (cstat & BIT_TMDS_CSTAT_P3_SCDT)
- sii8620_scdt_high(ctx);
+ if (cstat & BIT_TMDS_CSTAT_P3_SCDT) {
+ if (ctx->sink_type == SINK_HDMI)
+ /* enable infoframe interrupt */
+ sii8620_scdt_high(ctx);
+ else
+ sii8620_start_video(ctx);
+ }
}
sii8620_write(ctx, REG_INTR5, stat);
diff --git a/drivers/gpu/drm/bridge/sil-sii8620.h
b/drivers/gpu/drm/bridge/sil-sii8620.h
index 51ab540..c2f19b80 100644
--- a/drivers/gpu/drm/bridge/sil-sii8620.h
+++ b/drivers/gpu/drm/bridge/sil-sii8620.h
@@ -554,6 +554,7 @@
#define REG_RX_HDMI_CTRL2 0x02a3
#define MSK_RX_HDMI_CTRL2_IDLE_CNT 0xf0
#define VAL_RX_HDMI_CTRL2_IDLE_CNT(n) ((n) << 4)
+#define VAL_RX_HDMI_CTRL2_DEFVAL_DVI 0x30
#define BIT_RX_HDMI_CTRL2_USE_AV_MUTE BIT(3)
#define BIT_RX_HDMI_CTRL2_VSI_MON_SEL_VSI BIT(0)
@@ -1024,6 +1025,7 @@
#define BIT_TPI_SC_TPI_AV_MUTE BIT(3)
#define BIT_TPI_SC_DDC_GPU_REQUEST BIT(2)
#define BIT_TPI_SC_DDC_TPI_SW BIT(1)
+#define BIT_TPI_SC_TPI_OUTPUT_MODE_0_DVI BIT(1)
#define BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI BIT(0)
/* TPI COPP Query Data, default value: 0x00 */
--
2.7.4
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