On 22/10/17 12:13 AM, Petrosyan, Ludwig wrote: > But at first sight it has to be simple: > The PCIe Write transactions are address routed, so if in the packet header > the other endpoint address is written the TLP has to be routed (by PCIe > Switch to the endpoint), the DMA reading from the end point is really write > transactions from the endpoint, usually (Xilinx core) to start DMA one has to > write to the DMA control register of the endpoint the destination address. So > I have change the device driver to set in this register the physical address > of the other endpoint (get_resource start called to other endpoint, and it is > the same address which I could see in lspci -vvvv -s bus-address of the > switch port, memories behind bridge), so now the endpoint has to start send > writes TLP with the other endpoint address in the TLP header. > But this is not working (I want to understand why ...), but I could see the > first address of the destination endpoint is changed (with the wrong value > 0xFF), > now I want to try prepare in the driver of one endpoint the DMA buffer , but > using physical address of the other endpoint, > Could be it will never work, but I want to understand why, there is my error > ...
Hmm, well if I understand you correctly it sounds like, in theory, it should work. But there could be any number of reasons why it does not. You may need to get a hold of a PCIe analyzer to figure out what's actually going on. Logan _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
