Hi, On Fri, Oct 13, 2017 at 05:59:26PM +0300, Laurent Pinchart wrote: > The DSS private data structure is currently stored as a global variable. > While no platform with multiple DSS devices currently exists nor is > planned, this doesn't comply with the kernel device model and should > thus be fixed. > > As a first step to the fix, allocate the DSS private data structure > dynamically for each DSS instance. The pointer still needs to be stored > in a global variable as many functions exposed outside of the dss module > don't have access to the DSS private data structure. This will be fixed > in subsequent steps. > > Signed-off-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com> > ---
Reviewed-by: Sebastian Reichel <sebastian.reic...@collabora.co.uk>
-- Sebastian
> drivers/gpu/drm/omapdrm/dss/dss.c | 385
> +++++++++++++++++++++-----------------
> 1 file changed, 209 insertions(+), 176 deletions(-)
>
> diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c
> b/drivers/gpu/drm/omapdrm/dss/dss.c
> index 8b83bdcde6e2..8fec9bf6f06f 100644
> --- a/drivers/gpu/drm/omapdrm/dss/dss.c
> +++ b/drivers/gpu/drm/omapdrm/dss/dss.c
> @@ -67,11 +67,12 @@ struct dss_reg {
> #define DSS_PLL_CONTROL DSS_REG(0x0048)
> #define DSS_SDI_STATUS DSS_REG(0x005C)
>
> -#define REG_GET(idx, start, end) \
> - FLD_GET(dss_read_reg(idx), start, end)
> +#define REG_GET(dss, idx, start, end) \
> + FLD_GET(dss_read_reg(dss, idx), start, end)
>
> -#define REG_FLD_MOD(idx, val, start, end) \
> - dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
> +#define REG_FLD_MOD(dss, idx, val, start, end) \
> + dss_write_reg(dss, idx, \
> + FLD_MOD(dss_read_reg(dss, idx), val, start, end))
>
> struct dss_ops {
> int (*dpi_select_source)(struct dss_device *dss, int port,
> @@ -129,8 +130,6 @@ struct dss_device {
> struct dss_pll *video2_pll;
> };
>
> -static struct dss_device dss;
> -
> static const char * const dss_generic_clk_source_names[] = {
> [DSS_CLK_SRC_FCK] = "FCK",
> [DSS_CLK_SRC_PLL1_1] = "PLL1:1",
> @@ -142,49 +141,50 @@ static const char * const
> dss_generic_clk_source_names[] = {
> [DSS_CLK_SRC_HDMI_PLL] = "HDMI PLL",
> };
>
> -static inline void dss_write_reg(const struct dss_reg idx, u32 val)
> +static inline void dss_write_reg(struct dss_device *dss,
> + const struct dss_reg idx, u32 val)
> {
> - __raw_writel(val, dss.base + idx.idx);
> + __raw_writel(val, dss->base + idx.idx);
> }
>
> -static inline u32 dss_read_reg(const struct dss_reg idx)
> +static inline u32 dss_read_reg(struct dss_device *dss, const struct dss_reg
> idx)
> {
> - return __raw_readl(dss.base + idx.idx);
> + return __raw_readl(dss->base + idx.idx);
> }
>
> -#define SR(reg) \
> - dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
> -#define RR(reg) \
> - dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
> +#define SR(dss, reg) \
> + dss->ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(dss, DSS_##reg)
> +#define RR(dss, reg) \
> + dss_write_reg(dss, DSS_##reg, dss->ctx[(DSS_##reg).idx / sizeof(u32)])
>
> -static void dss_save_context(void)
> +static void dss_save_context(struct dss_device *dss)
> {
> DSSDBG("dss_save_context\n");
>
> - SR(CONTROL);
> + SR(dss, CONTROL);
>
> - if (dss.feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
> - SR(SDI_CONTROL);
> - SR(PLL_CONTROL);
> + if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
> + SR(dss, SDI_CONTROL);
> + SR(dss, PLL_CONTROL);
> }
>
> - dss.ctx_valid = true;
> + dss->ctx_valid = true;
>
> DSSDBG("context saved\n");
> }
>
> -static void dss_restore_context(void)
> +static void dss_restore_context(struct dss_device *dss)
> {
> DSSDBG("dss_restore_context\n");
>
> - if (!dss.ctx_valid)
> + if (!dss->ctx_valid)
> return;
>
> - RR(CONTROL);
> + RR(dss, CONTROL);
>
> - if (dss.feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
> - RR(SDI_CONTROL);
> - RR(PLL_CONTROL);
> + if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
> + RR(dss, SDI_CONTROL);
> + RR(dss, PLL_CONTROL);
> }
>
> DSSDBG("context restored\n");
> @@ -223,12 +223,13 @@ void dss_ctrl_pll_enable(struct dss_pll *pll, bool
> enable)
> 1 << shift, val << shift);
> }
>
> -static int dss_ctrl_pll_set_control_mux(enum dss_clk_source clk_src,
> - enum omap_channel channel)
> +static int dss_ctrl_pll_set_control_mux(struct dss_device *dss,
> + enum dss_clk_source clk_src,
> + enum omap_channel channel)
> {
> unsigned int shift, val;
>
> - if (!dss.syscon_pll_ctrl)
> + if (!dss->syscon_pll_ctrl)
> return -EINVAL;
>
> switch (channel) {
> @@ -283,7 +284,7 @@ static int dss_ctrl_pll_set_control_mux(enum
> dss_clk_source clk_src,
> return -EINVAL;
> }
>
> - regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset,
> + regmap_update_bits(dss->syscon_pll_ctrl, dss->syscon_pll_ctrl_offset,
> 0x3 << shift, val << shift);
>
> return 0;
> @@ -295,17 +296,17 @@ void dss_sdi_init(struct dss_device *dss, int datapairs)
>
> BUG_ON(datapairs > 3 || datapairs < 1);
>
> - l = dss_read_reg(DSS_SDI_CONTROL);
> + l = dss_read_reg(dss, DSS_SDI_CONTROL);
> l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
> l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
> l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
> - dss_write_reg(DSS_SDI_CONTROL, l);
> + dss_write_reg(dss, DSS_SDI_CONTROL, l);
>
> - l = dss_read_reg(DSS_PLL_CONTROL);
> + l = dss_read_reg(dss, DSS_PLL_CONTROL);
> l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
> l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
> l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
> - dss_write_reg(DSS_PLL_CONTROL, l);
> + dss_write_reg(dss, DSS_PLL_CONTROL, l);
> }
>
> int dss_sdi_enable(struct dss_device *dss)
> @@ -315,15 +316,15 @@ int dss_sdi_enable(struct dss_device *dss)
> dispc_pck_free_enable(1);
>
> /* Reset SDI PLL */
> - REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
> + REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
> udelay(1); /* wait 2x PCLK */
>
> /* Lock SDI PLL */
> - REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
> + REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
>
> /* Waiting for PLL lock request to complete */
> timeout = jiffies + msecs_to_jiffies(500);
> - while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
> + while (dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 6)) {
> if (time_after_eq(jiffies, timeout)) {
> DSSERR("PLL lock request timed out\n");
> goto err1;
> @@ -331,11 +332,11 @@ int dss_sdi_enable(struct dss_device *dss)
> }
>
> /* Clearing PLL_GO bit */
> - REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
> + REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 28, 28);
>
> /* Waiting for PLL to lock */
> timeout = jiffies + msecs_to_jiffies(500);
> - while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
> + while (!(dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 5))) {
> if (time_after_eq(jiffies, timeout)) {
> DSSERR("PLL lock timed out\n");
> goto err1;
> @@ -346,7 +347,7 @@ int dss_sdi_enable(struct dss_device *dss)
>
> /* Waiting for SDI reset to complete */
> timeout = jiffies + msecs_to_jiffies(500);
> - while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
> + while (!(dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 2))) {
> if (time_after_eq(jiffies, timeout)) {
> DSSERR("SDI reset timed out\n");
> goto err2;
> @@ -359,7 +360,7 @@ int dss_sdi_enable(struct dss_device *dss)
> dispc_lcd_enable_signal(0);
> err1:
> /* Reset SDI PLL */
> - REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
> + REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
>
> dispc_pck_free_enable(0);
>
> @@ -373,7 +374,7 @@ void dss_sdi_disable(struct dss_device *dss)
> dispc_pck_free_enable(0);
>
> /* Reset SDI PLL */
> - REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
> + REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
> }
>
> const char *dss_get_clk_source_name(enum dss_clk_source clk_src)
> @@ -382,46 +383,48 @@ const char *dss_get_clk_source_name(enum dss_clk_source
> clk_src)
> }
>
> #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
> -static void dss_dump_clocks(struct seq_file *s)
> +static void dss_dump_clocks(struct dss_device *dss, struct seq_file *s)
> {
> const char *fclk_name;
> unsigned long fclk_rate;
>
> - if (dss_runtime_get(&dss))
> + if (dss_runtime_get(dss))
> return;
>
> seq_printf(s, "- DSS -\n");
>
> fclk_name = dss_get_clk_source_name(DSS_CLK_SRC_FCK);
> - fclk_rate = clk_get_rate(dss.dss_clk);
> + fclk_rate = clk_get_rate(dss->dss_clk);
>
> seq_printf(s, "%s = %lu\n",
> fclk_name,
> fclk_rate);
>
> - dss_runtime_put(&dss);
> + dss_runtime_put(dss);
> }
> #endif
>
> static int dss_dump_regs(struct seq_file *s, void *p)
> {
> -#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
> + struct dss_device *dss = s->private;
> +
> +#define DUMPREG(dss, r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(dss,
> r))
>
> - if (dss_runtime_get(&dss))
> + if (dss_runtime_get(dss))
> return 0;
>
> - DUMPREG(DSS_REVISION);
> - DUMPREG(DSS_SYSCONFIG);
> - DUMPREG(DSS_SYSSTATUS);
> - DUMPREG(DSS_CONTROL);
> + DUMPREG(dss, DSS_REVISION);
> + DUMPREG(dss, DSS_SYSCONFIG);
> + DUMPREG(dss, DSS_SYSSTATUS);
> + DUMPREG(dss, DSS_CONTROL);
>
> - if (dss.feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
> - DUMPREG(DSS_SDI_CONTROL);
> - DUMPREG(DSS_PLL_CONTROL);
> - DUMPREG(DSS_SDI_STATUS);
> + if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
> + DUMPREG(dss, DSS_SDI_CONTROL);
> + DUMPREG(dss, DSS_PLL_CONTROL);
> + DUMPREG(dss, DSS_SDI_STATUS);
> }
>
> - dss_runtime_put(&dss);
> + dss_runtime_put(dss);
> #undef DUMPREG
> return 0;
> }
> @@ -441,7 +444,8 @@ static int dss_get_channel_index(enum omap_channel
> channel)
> }
> }
>
> -static void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
> +static void dss_select_dispc_clk_source(struct dss_device *dss,
> + enum dss_clk_source clk_src)
> {
> int b;
>
> @@ -449,7 +453,7 @@ static void dss_select_dispc_clk_source(enum
> dss_clk_source clk_src)
> * We always use PRCM clock as the DISPC func clock, except on DSS3,
> * where we don't have separate DISPC and LCD clock sources.
> */
> - if (WARN_ON(dss.feat->has_lcd_clk_src && clk_src != DSS_CLK_SRC_FCK))
> + if (WARN_ON(dss->feat->has_lcd_clk_src && clk_src != DSS_CLK_SRC_FCK))
> return;
>
> switch (clk_src) {
> @@ -467,11 +471,11 @@ static void dss_select_dispc_clk_source(enum
> dss_clk_source clk_src)
> return;
> }
>
> - REG_FLD_MOD(DSS_CONTROL, b, /* DISPC_CLK_SWITCH */
> - dss.feat->dispc_clk_switch.start,
> - dss.feat->dispc_clk_switch.end);
> + REG_FLD_MOD(dss, DSS_CONTROL, b, /* DISPC_CLK_SWITCH */
> + dss->feat->dispc_clk_switch.start,
> + dss->feat->dispc_clk_switch.end);
>
> - dss.dispc_clk_source = clk_src;
> + dss->dispc_clk_source = clk_src;
> }
>
> void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module,
> @@ -497,7 +501,7 @@ void dss_select_dsi_clk_source(struct dss_device *dss,
> int dsi_module,
> }
>
> pos = dsi_module == 0 ? 1 : 10;
> - REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */
> + REG_FLD_MOD(dss, DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */
>
> dss->dsi_clk_source[dsi_module] = clk_src;
> }
> @@ -517,15 +521,15 @@ static int dss_lcd_clk_mux_dra7(struct dss_device *dss,
>
> if (clk_src == DSS_CLK_SRC_FCK) {
> /* LCDx_CLK_SWITCH */
> - REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
> + REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
> return -EINVAL;
> }
>
> - r = dss_ctrl_pll_set_control_mux(clk_src, channel);
> + r = dss_ctrl_pll_set_control_mux(dss, clk_src, channel);
> if (r)
> return r;
>
> - REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
> + REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
>
> return 0;
> }
> @@ -549,14 +553,14 @@ static int dss_lcd_clk_mux_omap5(struct dss_device *dss,
>
> if (clk_src == DSS_CLK_SRC_FCK) {
> /* LCDx_CLK_SWITCH */
> - REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
> + REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
> return -EINVAL;
> }
>
> if (WARN_ON(allowed_plls[channel] != clk_src))
> return -EINVAL;
>
> - REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
> + REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
>
> return 0;
> }
> @@ -578,14 +582,14 @@ static int dss_lcd_clk_mux_omap4(struct dss_device *dss,
>
> if (clk_src == DSS_CLK_SRC_FCK) {
> /* LCDx_CLK_SWITCH */
> - REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
> + REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
> return 0;
> }
>
> if (WARN_ON(allowed_plls[channel] != clk_src))
> return -EINVAL;
>
> - REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
> + REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
>
> return 0;
> }
> @@ -598,7 +602,7 @@ void dss_select_lcd_clk_source(struct dss_device *dss,
> int r;
>
> if (!dss->feat->has_lcd_clk_src) {
> - dss_select_dispc_clk_source(clk_src);
> + dss_select_dispc_clk_source(dss, clk_src);
> dss->lcd_clk_source[idx] = clk_src;
> return;
> }
> @@ -712,26 +716,26 @@ enum omap_dss_output_id
> dss_get_supported_outputs(struct dss_device *dss,
> return dss->feat->outputs[channel];
> }
>
> -static int dss_setup_default_clock(void)
> +static int dss_setup_default_clock(struct dss_device *dss)
> {
> unsigned long max_dss_fck, prate;
> unsigned long fck;
> unsigned int fck_div;
> int r;
>
> - max_dss_fck = dss.feat->fck_freq_max;
> + max_dss_fck = dss->feat->fck_freq_max;
>
> - if (dss.parent_clk == NULL) {
> - fck = clk_round_rate(dss.dss_clk, max_dss_fck);
> + if (dss->parent_clk == NULL) {
> + fck = clk_round_rate(dss->dss_clk, max_dss_fck);
> } else {
> - prate = clk_get_rate(dss.parent_clk);
> + prate = clk_get_rate(dss->parent_clk);
>
> - fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
> + fck_div = DIV_ROUND_UP(prate * dss->feat->dss_fck_multiplier,
> max_dss_fck);
> - fck = DIV_ROUND_UP(prate, fck_div) *
> dss.feat->dss_fck_multiplier;
> + fck = DIV_ROUND_UP(prate, fck_div) *
> dss->feat->dss_fck_multiplier;
> }
>
> - r = dss_set_fck_rate(&dss, fck);
> + r = dss_set_fck_rate(dss, fck);
> if (r)
> return r;
>
> @@ -750,12 +754,13 @@ void dss_set_venc_output(struct dss_device *dss, enum
> omap_dss_venc_type type)
> BUG();
>
> /* venc out selection. 0 = comp, 1 = svideo */
> - REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
> + REG_FLD_MOD(dss, DSS_CONTROL, l, 6, 6);
> }
>
> void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable)
> {
> - REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
> + /* DAC Power-Down Control */
> + REG_FLD_MOD(dss, DSS_CONTROL, enable, 5, 5);
> }
>
> void dss_select_hdmi_venc_clk_source(struct dss_device *dss,
> @@ -772,7 +777,8 @@ void dss_select_hdmi_venc_clk_source(struct dss_device
> *dss,
> /* Select only if we have options */
> if ((outputs & OMAP_DSS_OUTPUT_VENC) &&
> (outputs & OMAP_DSS_OUTPUT_HDMI))
> - REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */
> + /* VENC_HDMI_SWITCH */
> + REG_FLD_MOD(dss, DSS_CONTROL, src, 15, 15);
> }
>
> static int dss_dpi_select_source_omap2_omap3(struct dss_device *dss, int
> port,
> @@ -800,7 +806,7 @@ static int dss_dpi_select_source_omap4(struct dss_device
> *dss, int port,
> return -EINVAL;
> }
>
> - REG_FLD_MOD(DSS_CONTROL, val, 17, 17);
> + REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 17);
>
> return 0;
> }
> @@ -827,7 +833,7 @@ static int dss_dpi_select_source_omap5(struct dss_device
> *dss, int port,
> return -EINVAL;
> }
>
> - REG_FLD_MOD(DSS_CONTROL, val, 17, 16);
> + REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 16);
>
> return 0;
> }
> @@ -859,37 +865,37 @@ int dss_dpi_select_source(struct dss_device *dss, int
> port,
> return dss->feat->ops->dpi_select_source(dss, port, channel);
> }
>
> -static int dss_get_clocks(void)
> +static int dss_get_clocks(struct dss_device *dss)
> {
> struct clk *clk;
>
> - clk = devm_clk_get(&dss.pdev->dev, "fck");
> + clk = devm_clk_get(&dss->pdev->dev, "fck");
> if (IS_ERR(clk)) {
> DSSERR("can't get clock fck\n");
> return PTR_ERR(clk);
> }
>
> - dss.dss_clk = clk;
> + dss->dss_clk = clk;
>
> - if (dss.feat->parent_clk_name) {
> - clk = clk_get(NULL, dss.feat->parent_clk_name);
> + if (dss->feat->parent_clk_name) {
> + clk = clk_get(NULL, dss->feat->parent_clk_name);
> if (IS_ERR(clk)) {
> - DSSERR("Failed to get %s\n", dss.feat->parent_clk_name);
> + DSSERR("Failed to get %s\n",
> dss->feat->parent_clk_name);
> return PTR_ERR(clk);
> }
> } else {
> clk = NULL;
> }
>
> - dss.parent_clk = clk;
> + dss->parent_clk = clk;
>
> return 0;
> }
>
> -static void dss_put_clocks(void)
> +static void dss_put_clocks(struct dss_device *dss)
> {
> - if (dss.parent_clk)
> - clk_put(dss.parent_clk);
> + if (dss->parent_clk)
> + clk_put(dss->parent_clk);
> }
>
> int dss_runtime_get(struct dss_device *dss)
> @@ -915,14 +921,16 @@ void dss_runtime_put(struct dss_device *dss)
>
> struct dss_device *dss_get_device(struct device *dev)
> {
> - return &dss;
> + return dev_get_drvdata(dev);
> }
>
> /* DEBUGFS */
> #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
> static int dss_debug_dump_clocks(struct seq_file *s, void *p)
> {
> - dss_dump_clocks(s);
> + struct dss_device *dss = s->private;
> +
> + dss_dump_clocks(dss, s);
> dispc_dump_clocks(s);
> #ifdef CONFIG_OMAP2_DSS_DSI
> dsi_dump_clocks(s);
> @@ -932,7 +940,7 @@ static int dss_debug_dump_clocks(struct seq_file *s, void
> *p)
>
> static struct dentry *dss_debugfs_dir;
>
> -static int dss_initialize_debugfs(void)
> +static int dss_initialize_debugfs(struct dss_device *dss)
> {
> dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
> if (IS_ERR(dss_debugfs_dir)) {
> @@ -1005,7 +1013,7 @@ void dss_debugfs_remove_file(struct dss_debugfs_entry
> *entry)
> }
>
> #else /* CONFIG_OMAP2_DSS_DEBUGFS */
> -static inline int dss_initialize_debugfs(void)
> +static inline int dss_initialize_debugfs(struct dss_device *dss)
> {
> return 0;
> }
> @@ -1210,23 +1218,24 @@ static const struct dss_features dra7xx_dss_feats = {
> .has_lcd_clk_src = true,
> };
>
> -static int dss_init_ports(struct platform_device *pdev)
> +static int dss_init_ports(struct dss_device *dss)
> {
> + struct platform_device *pdev = dss->pdev;
> struct device_node *parent = pdev->dev.of_node;
> struct device_node *port;
> int i;
>
> - for (i = 0; i < dss.feat->num_ports; i++) {
> + for (i = 0; i < dss->feat->num_ports; i++) {
> port = of_graph_get_port_by_id(parent, i);
> if (!port)
> continue;
>
> - switch (dss.feat->ports[i]) {
> + switch (dss->feat->ports[i]) {
> case OMAP_DISPLAY_TYPE_DPI:
> - dpi_init_port(&dss, pdev, port, dss.feat->model);
> + dpi_init_port(dss, pdev, port, dss->feat->model);
> break;
> case OMAP_DISPLAY_TYPE_SDI:
> - sdi_init_port(&dss, pdev, port);
> + sdi_init_port(dss, pdev, port);
> break;
> default:
> break;
> @@ -1236,18 +1245,19 @@ static int dss_init_ports(struct platform_device
> *pdev)
> return 0;
> }
>
> -static void dss_uninit_ports(struct platform_device *pdev)
> +static void dss_uninit_ports(struct dss_device *dss)
> {
> + struct platform_device *pdev = dss->pdev;
> struct device_node *parent = pdev->dev.of_node;
> struct device_node *port;
> int i;
>
> - for (i = 0; i < dss.feat->num_ports; i++) {
> + for (i = 0; i < dss->feat->num_ports; i++) {
> port = of_graph_get_port_by_id(parent, i);
> if (!port)
> continue;
>
> - switch (dss.feat->ports[i]) {
> + switch (dss->feat->ports[i]) {
> case OMAP_DISPLAY_TYPE_DPI:
> dpi_uninit_port(port);
> break;
> @@ -1260,8 +1270,9 @@ static void dss_uninit_ports(struct platform_device
> *pdev)
> }
> }
>
> -static int dss_video_pll_probe(struct platform_device *pdev)
> +static int dss_video_pll_probe(struct dss_device *dss)
> {
> + struct platform_device *pdev = dss->pdev;
> struct device_node *np = pdev->dev.of_node;
> struct regulator *pll_regulator;
> int r;
> @@ -1270,16 +1281,16 @@ static int dss_video_pll_probe(struct platform_device
> *pdev)
> return 0;
>
> if (of_property_read_bool(np, "syscon-pll-ctrl")) {
> - dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np,
> + dss->syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np,
> "syscon-pll-ctrl");
> - if (IS_ERR(dss.syscon_pll_ctrl)) {
> + if (IS_ERR(dss->syscon_pll_ctrl)) {
> dev_err(&pdev->dev,
> "failed to get syscon-pll-ctrl regmap\n");
> - return PTR_ERR(dss.syscon_pll_ctrl);
> + return PTR_ERR(dss->syscon_pll_ctrl);
> }
>
> if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1,
> - &dss.syscon_pll_ctrl_offset)) {
> + &dss->syscon_pll_ctrl_offset)) {
> dev_err(&pdev->dev,
> "failed to get syscon-pll-ctrl offset\n");
> return -EINVAL;
> @@ -1305,18 +1316,18 @@ static int dss_video_pll_probe(struct platform_device
> *pdev)
> }
>
> if (of_property_match_string(np, "reg-names", "pll1") >= 0) {
> - dss.video1_pll = dss_video_pll_init(&dss, pdev, 0,
> - pll_regulator);
> - if (IS_ERR(dss.video1_pll))
> - return PTR_ERR(dss.video1_pll);
> + dss->video1_pll = dss_video_pll_init(dss, pdev, 0,
> + pll_regulator);
> + if (IS_ERR(dss->video1_pll))
> + return PTR_ERR(dss->video1_pll);
> }
>
> if (of_property_match_string(np, "reg-names", "pll2") >= 0) {
> - dss.video2_pll = dss_video_pll_init(&dss, pdev, 1,
> - pll_regulator);
> - if (IS_ERR(dss.video2_pll)) {
> - dss_video_pll_uninit(dss.video1_pll);
> - return PTR_ERR(dss.video2_pll);
> + dss->video2_pll = dss_video_pll_init(dss, pdev, 1,
> + pll_regulator);
> + if (IS_ERR(dss->video2_pll)) {
> + dss_video_pll_uninit(dss->video1_pll);
> + return PTR_ERR(dss->video2_pll);
> }
> }
>
> @@ -1344,117 +1355,119 @@ static const struct soc_device_attribute
> dss_soc_devices[] = {
> static int dss_bind(struct device *dev)
> {
> struct platform_device *pdev = to_platform_device(dev);
> + struct dss_device *dss = dev_get_drvdata(dev);
> struct resource *dss_mem;
> u32 rev;
> int r;
>
> - dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
> - dss.base = devm_ioremap_resource(&pdev->dev, dss_mem);
> - if (IS_ERR(dss.base))
> - return PTR_ERR(dss.base);
> + dss_mem = platform_get_resource(dss->pdev, IORESOURCE_MEM, 0);
> + dss->base = devm_ioremap_resource(&pdev->dev, dss_mem);
> + if (IS_ERR(dss->base))
> + return PTR_ERR(dss->base);
>
> - r = dss_get_clocks();
> + r = dss_get_clocks(dss);
> if (r)
> return r;
>
> - r = dss_setup_default_clock();
> + r = dss_setup_default_clock(dss);
> if (r)
> goto err_setup_clocks;
>
> - r = dss_video_pll_probe(pdev);
> + r = dss_video_pll_probe(dss);
> if (r)
> goto err_pll_init;
>
> - r = dss_init_ports(pdev);
> + r = dss_init_ports(dss);
> if (r)
> goto err_init_ports;
>
> pm_runtime_enable(&pdev->dev);
>
> - r = dss_runtime_get(&dss);
> + r = dss_runtime_get(dss);
> if (r)
> goto err_runtime_get;
>
> - dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
> + dss->dss_clk_rate = clk_get_rate(dss->dss_clk);
>
> /* Select DPLL */
> - REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
> + REG_FLD_MOD(dss, DSS_CONTROL, 0, 0, 0);
>
> - dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
> + dss_select_dispc_clk_source(dss, DSS_CLK_SRC_FCK);
>
> #ifdef CONFIG_OMAP2_DSS_VENC
> - REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
> - REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
> - REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
> + REG_FLD_MOD(dss, DSS_CONTROL, 1, 4, 4); /* venc dac demen */
> + REG_FLD_MOD(dss, DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
> + REG_FLD_MOD(dss, DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
> #endif
> - dss.dsi_clk_source[0] = DSS_CLK_SRC_FCK;
> - dss.dsi_clk_source[1] = DSS_CLK_SRC_FCK;
> - dss.dispc_clk_source = DSS_CLK_SRC_FCK;
> - dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK;
> - dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK;
> + dss->dsi_clk_source[0] = DSS_CLK_SRC_FCK;
> + dss->dsi_clk_source[1] = DSS_CLK_SRC_FCK;
> + dss->dispc_clk_source = DSS_CLK_SRC_FCK;
> + dss->lcd_clk_source[0] = DSS_CLK_SRC_FCK;
> + dss->lcd_clk_source[1] = DSS_CLK_SRC_FCK;
>
> - rev = dss_read_reg(DSS_REVISION);
> + rev = dss_read_reg(dss, DSS_REVISION);
> pr_info("OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
>
> - dss_runtime_put(&dss);
> + dss_runtime_put(dss);
>
> r = component_bind_all(&pdev->dev, NULL);
> if (r)
> goto err_component;
>
> - dss.debugfs.clk = dss_debugfs_create_file("clk", dss_debug_dump_clocks,
> - &dss);
> - dss.debugfs.dss = dss_debugfs_create_file("dss", dss_dump_regs, &dss);
> + dss->debugfs.clk = dss_debugfs_create_file("clk", dss_debug_dump_clocks,
> + dss);
> + dss->debugfs.dss = dss_debugfs_create_file("dss", dss_dump_regs, dss);
>
> pm_set_vt_switch(0);
>
> omapdss_gather_components(dev);
>
> - r = omapdrm_init(&dss.drm, dev);
> + r = omapdrm_init(&dss->drm, dev);
> if (r)
> goto err_drm_init;
>
> return 0;
>
> err_drm_init:
> - dss_debugfs_remove_file(dss.debugfs.clk);
> - dss_debugfs_remove_file(dss.debugfs.dss);
> + dss_debugfs_remove_file(dss->debugfs.clk);
> + dss_debugfs_remove_file(dss->debugfs.dss);
> component_unbind_all(&pdev->dev, NULL);
> err_component:
> err_runtime_get:
> pm_runtime_disable(&pdev->dev);
> - dss_uninit_ports(pdev);
> + dss_uninit_ports(dss);
> err_init_ports:
> - if (dss.video1_pll)
> - dss_video_pll_uninit(dss.video1_pll);
> + if (dss->video1_pll)
> + dss_video_pll_uninit(dss->video1_pll);
>
> - if (dss.video2_pll)
> - dss_video_pll_uninit(dss.video2_pll);
> + if (dss->video2_pll)
> + dss_video_pll_uninit(dss->video2_pll);
> err_pll_init:
> err_setup_clocks:
> - dss_put_clocks();
> + dss_put_clocks(dss);
> return r;
> }
>
> static void dss_unbind(struct device *dev)
> {
> struct platform_device *pdev = to_platform_device(dev);
> + struct dss_device *dss = dev_get_drvdata(dev);
>
> - omapdrm_cleanup(&dss.drm);
> + omapdrm_cleanup(&dss->drm);
>
> component_unbind_all(&pdev->dev, NULL);
>
> - if (dss.video1_pll)
> - dss_video_pll_uninit(dss.video1_pll);
> + if (dss->video1_pll)
> + dss_video_pll_uninit(dss->video1_pll);
>
> - if (dss.video2_pll)
> - dss_video_pll_uninit(dss.video2_pll);
> + if (dss->video2_pll)
> + dss_video_pll_uninit(dss->video2_pll);
>
> - dss_uninit_ports(pdev);
> + dss_uninit_ports(dss);
>
> pm_runtime_disable(&pdev->dev);
>
> - dss_put_clocks();
> + dss_put_clocks(dss);
> }
>
> static const struct component_master_ops dss_component_ops = {
> @@ -1490,14 +1503,20 @@ static int dss_probe(struct platform_device *pdev)
> {
> const struct soc_device_attribute *soc;
> struct component_match *match = NULL;
> + struct dss_device *dss;
> int r;
>
> - dss.pdev = pdev;
> + dss = kzalloc(sizeof(*dss), GFP_KERNEL);
> + if (!dss)
> + return -ENOMEM;
> +
> + dss->pdev = pdev;
> + platform_set_drvdata(pdev, dss);
>
> r = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
> if (r) {
> dev_err(&pdev->dev, "Failed to set the DMA mask\n");
> - return r;
> + goto err_free_dss;
> }
>
> /*
> @@ -1506,31 +1525,38 @@ static int dss_probe(struct platform_device *pdev)
> */
> soc = soc_device_match(dss_soc_devices);
> if (soc)
> - dss.feat = soc->data;
> + dss->feat = soc->data;
> else
> - dss.feat = of_match_device(dss_of_match, &pdev->dev)->data;
> + dss->feat = of_match_device(dss_of_match, &pdev->dev)->data;
>
> - r = dss_initialize_debugfs();
> + r = dss_initialize_debugfs(dss);
> if (r)
> - return r;
> + goto err_free_dss;
>
> /* add all the child devices as components */
> device_for_each_child(&pdev->dev, &match, dss_add_child_component);
>
> r = component_master_add_with_match(&pdev->dev, &dss_component_ops,
> match);
> - if (r) {
> - dss_uninitialize_debugfs();
> - return r;
> - }
> + if (r)
> + goto err_debugfs;
>
> return 0;
> +
> +err_debugfs:
> + dss_uninitialize_debugfs();
> +err_free_dss:
> + kfree(dss);
> + return r;
> }
>
> static int dss_remove(struct platform_device *pdev)
> {
> + struct dss_device *dss = platform_get_drvdata(pdev);
> +
> component_master_del(&pdev->dev, &dss_component_ops);
>
> dss_uninitialize_debugfs();
> + kfree(dss);
>
> return 0;
> }
> @@ -1552,7 +1578,9 @@ static void dss_shutdown(struct platform_device *pdev)
>
> static int dss_runtime_suspend(struct device *dev)
> {
> - dss_save_context();
> + struct dss_device *dss = dev_get_drvdata(dev);
> +
> + dss_save_context(dss);
> dss_set_min_bus_tput(dev, 0);
>
> pinctrl_pm_select_sleep_state(dev);
> @@ -1562,6 +1590,7 @@ static int dss_runtime_suspend(struct device *dev)
>
> static int dss_runtime_resume(struct device *dev)
> {
> + struct dss_device *dss = dev_get_drvdata(dev);
> int r;
>
> pinctrl_pm_select_default_state(dev);
> @@ -1577,18 +1606,22 @@ static int dss_runtime_resume(struct device *dev)
> if (r)
> return r;
>
> - dss_restore_context();
> + dss_restore_context(dss);
> return 0;
> }
>
> static int dss_suspend(struct device *dev)
> {
> - return omap_drm_suspend(&dss.drm);
> + struct dss_device *dss = dev_get_drvdata(dev);
> +
> + return omap_drm_suspend(&dss->drm);
> }
>
> static int dss_resume(struct device *dev)
> {
> - return omap_drm_resume(&dss.drm);
> + struct dss_device *dss = dev_get_drvdata(dev);
> +
> + return omap_drm_resume(&dss->drm);
> }
>
> static const struct dev_pm_ops dss_pm_ops = {
> --
> Regards,
>
> Laurent Pinchart
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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