Save the GMBUS2 value read while polling for state changes, and then
reuse this value when determining for which reason the loops were exited.
This is a small optimization which saves a couple of bus accesses for
memory mapped IO registers.
Signed-off-by: Daniel Kurtz <djku...@chromium.org>
Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_i2c.c | 19 ++++++++++---------
1 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 61fe317..2c372d3 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -243,6 +243,7 @@ gmbus_xfer(struct i2c_adapter *adapter,
struct drm_i915_private *dev_priv = adapter->algo_data;
int i, reg_offset;
int ret = 0;
+ u32 gmbus2 = 0;
if (bus->force_bit)
return intel_i2c_quirk_xfer(dev_priv,
@@ -296,12 +297,12 @@ gmbus_xfer(struct i2c_adapter *adapter,
do {
u32 val, loop = 0;
- if (wait_for(I915_READ(GMBUS2 + reg_offset) &
+ if (wait_for((gmbus2 = I915_READ(GMBUS2 +
+ reg_offset)) &
(GMBUS_SATOER | GMBUS_HW_RDY),
50))
goto timeout;
- if (I915_READ(GMBUS2 + reg_offset) &
- GMBUS_SATOER)
+ if (gmbus2 & GMBUS_SATOER)
goto clear_err;
val = I915_READ(GMBUS3 + reg_offset);
@@ -335,21 +336,21 @@ gmbus_xfer(struct i2c_adapter *adapter,
I915_WRITE(GMBUS3 + reg_offset, val);
POSTING_READ(GMBUS2 + reg_offset);
- if (wait_for(I915_READ(GMBUS2 + reg_offset) &
+ if (wait_for((gmbus2 = I915_READ(GMBUS2 +
+ reg_offset)) &
(GMBUS_SATOER | GMBUS_HW_RDY),
50))
goto timeout;
- if (I915_READ(GMBUS2 + reg_offset) &
- GMBUS_SATOER)
+ if (gmbus2 & GMBUS_SATOER)
goto clear_err;
}
}
- if (wait_for(I915_READ(GMBUS2 + reg_offset) &
+ if (wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
(GMBUS_SATOER | GMBUS_HW_WAIT_PHASE),
50))
goto timeout;
- if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
+ if (gmbus2 & GMBUS_SATOER)
goto clear_err;
}
@@ -373,7 +374,7 @@ clear_err:
ret = -ENXIO;
done:
- if (I915_READ(GMBUS2 + reg_offset) & GMBUS_HW_WAIT_PHASE) {
+ if (gmbus2 & GMBUS_HW_WAIT_PHASE) {
I915_WRITE(GMBUS1 + reg_offset,
GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
POSTING_READ(GMBUS2 + reg_offset);
--
1.7.7.3
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