The code attempts to enable them, but hits an undefined behaviour by
shifting by the entire register's width:
int lines = 32;
u32 mask = (1 << lines) - 1; // 00000000 on x86
u32 mask = (1 << lines) - 1; // ffffffff on arm (32)
u32 mask = (1 << lines) - 1; // 00000000 on arm64
u32 mask = (1ULL << lines) - 1; // ffffffff everywhere
Signed-off-by: Adam Borowski <kilob...@angband.pl>
---
To be honest, I can't tell the difference other than UBSAN stopping its
complaints, but the current code is obviously wrong.
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
index 77c649723ad7..4a57defc99b3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
@@ -164,7 +164,7 @@ static int
nvkm_gpio_fini(struct nvkm_subdev *subdev, bool suspend)
{
struct nvkm_gpio *gpio = nvkm_gpio(subdev);
- u32 mask = (1 << gpio->func->lines) - 1;
+ u32 mask = (1ULL << gpio->func->lines) - 1;
gpio->func->intr_mask(gpio, NVKM_GPIO_TOGGLED, mask, 0);
gpio->func->intr_stat(gpio, &mask, &mask);
--
2.11.0
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