On 06/09/16 11:19, Jyri Sarha wrote:
> +static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct tilcdc_drm_private *priv = dev->dev_private;
> + struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
> + const unsigned clkdiv = 2; /* using a fixed divider of 2 */
Btw, not related to this patch, but you may want to revisit this
hardcoded divider at some point. I don't remember the history, but it
was a quick solution to some issues. Supporting any divider the HW
allows would probably give us better clock rates.
Well, except if the source clock comes right from a dedicated PLL, which
supports the whole pixel clock range. If that's the case, then the LCDC
divider doesn't help much.
Tomi
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