[PATCH 2/2] drm/i915/gvt: fix compilation

[Arnd Bergmann]

Two functions in the newly added gvt render code are obviously
broken, as they reference a variable without initialization and
don't reference another variable at all:

drivers/gpu/drm/i915/gvt/render.c: In function ‘intel_gvt_load_render_mmio’:
drivers/gpu/drm/i915/gvt/render.c:148:13: error: ‘offset.reg’ may be used 
uninitialized in this function [-Werror=maybe-uninitialized]
drivers/gpu/drm/i915/gvt/render.c: In function 
‘intel_gvt_restore_render_mmio’:
drivers/gpu/drm/i915/gvt/render.c:185:13: error: ‘offset.reg’ may be used 
uninitialized in this function [-Werror=maybe-uninitialized]

This is probably not a correct fix, but it gets us a clean build
by removing the unused arrays and initializing the offset variable
to something that potentially might be correct.

Fixes: 178657139307 ("drm/i915/gvt: vGPU context switch")
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/gpu/drm/i915/gvt/render.c | 25 +++----------------------
 1 file changed, 3 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/render.c 
b/drivers/gpu/drm/i915/gvt/render.c
index feebb65ba641..79e112288065 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -147,29 +147,20 @@ static void load_mocs(struct intel_vgpu *vgpu, int 
ring_id)
 {
        struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
        i915_reg_t offset, l3_offset;
-       u32 regs[] = {
-               [RCS] = 0xc800,
-               [VCS] = 0xc900,
-               [VCS2] = 0xca00,
-               [BCS] = 0xcc00,
-               [VECS] = 0xcb00,
-       };
        int i;

-       if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
-               return;
-
        if (!IS_SKYLAKE(dev_priv))
                return;

        for (i = 0; i < 64; i++) {
+               offset.reg = i * 4;
                gen9_render_mocs[ring_id][i] = I915_READ(offset);
                I915_WRITE(offset, vgpu_vreg(vgpu, offset));
                POSTING_READ(offset);
-               offset.reg += 4;
        }

        if (ring_id == RCS) {
+               offset.reg = 64 * 4;
                l3_offset.reg = 0xb020;
                for (i = 0; i < 32; i++) {
                        gen9_render_mocs_L3[i] = I915_READ(l3_offset);
@@ -184,26 +175,16 @@ static void restore_mocs(struct intel_vgpu *vgpu, int 
ring_id)
 {
        struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
        i915_reg_t offset, l3_offset;
-       u32 regs[] = {
-               [RCS] = 0xc800,
-               [VCS] = 0xc900,
-               [VCS2] = 0xca00,
-               [BCS] = 0xcc00,
-               [VECS] = 0xcb00,
-       };
        int i;

-       if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
-               return;
-
        if (!IS_SKYLAKE(dev_priv))
                return;

        for (i = 0; i < 64; i++) {
+               offset.reg = i * 4;
                vgpu_vreg(vgpu, offset) = I915_READ(offset);
                I915_WRITE(offset, gen9_render_mocs[ring_id][i]);
                POSTING_READ(offset);
-               offset.reg += 4;
        }

        if (ring_id == RCS) {
-- 
2.9.0