[PATCH 11/10] drm/etnaviv: HACK: enable debug register

[Christian Gmeiner]

I am not sure how the correct solution should look like.
Maybe enable debug registers globally via not existing
SET_PARAM ioctl.

Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
---
 drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c 
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index b3eba08..6d9bfdf 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -428,8 +428,7 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
        timeout = jiffies + msecs_to_jiffies(1000);

        while (time_is_after_jiffies(timeout)) {
-               control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
-                         VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
+               control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);

                /* enable clock */
                etnaviv_gpu_load_clock(gpu, control);
@@ -492,8 +491,7 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
        }

        /* We rely on the GPU running, so program the clock */
-       control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
-                 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
+       control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);

        /* enable clock */
        etnaviv_gpu_load_clock(gpu, control);
@@ -1561,8 +1559,7 @@ static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
        if (ret)
                return ret;

-       clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
-               VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
+       clock = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);

        etnaviv_gpu_load_clock(gpu, clock);
        etnaviv_gpu_hw_init(gpu);
-- 
2.10.2