From: Junzhi Zhao <junzhi.z...@mediatek.com>

Pixel clock should be 297MHz when resolution is 4K.

Signed-off-by: Junzhi Zhao <junzhi.zhao at mediatek.com>
Signed-off-by: Bibby Hsieh <bibby.hsieh at mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c |    8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index d05ca79..a90af59 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -438,10 +438,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
        }

        pix_rate = 1000UL * mode->clock;
-       if (mode->clock <= 74000)
+       if (mode->clock <= 27000)
+               factor = 16 * 3;
+       else if (mode->clock <= 74250)
                factor = 8 * 3;
-       else
+       else if (mode->clock <= 167000)
                factor = 4 * 3;
+       else
+               factor = 2 * 3;
        pll_rate = pix_rate * factor;

        dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
-- 
1.7.9.5

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