On 05.11.2015 20:06, Jay Cornwall wrote: > The VM default page (used when a VM translation fails) is allocated in > system memory. The VM is misconfigured to interpret the physical address > as referencing a VRAM physical page. > > Route default page accesses to system memory. > > Signed-off-by: Jay Cornwall <jay at jcornwall.me> > Cc: <stable at vger.kernel.org> # v4.2+
Nice catch, patch is Reviewed-by: Christian König <christian.koenig at amd.com> Do we also need this for Radeon? Regards, Christian. > --- > drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 + > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > index fab5471..b9836f6 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > @@ -474,6 +474,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device > *adev) > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, > ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, > ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); > WREG32(mmVM_L2_CNTL, tmp); > tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > index 7bc9e9f..cb4e2bb 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > @@ -588,6 +588,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device > *adev) > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, > ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, > ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); > WREG32(mmVM_L2_CNTL, tmp); > tmp = RREG32(mmVM_L2_CNTL2); > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
