Instead of allocating CTL for each CRTC, we start to associate CTL to each display interface, which reflects real HW requirement. It also helps in making use of HW single FLUSH feature to sync between dual DSI pipes.
Hai Li (2): drm/msm/mdp5: Allocate CTL for each display interface drm/msm/mdp5: Allocate CTL0/1 for dual DSI single FLUSH drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 12 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 26 +--- drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 179 ++++++++++++++++++------ drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h | 13 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 18 ++- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 38 +++-- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 8 +- 7 files changed, 200 insertions(+), 94 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
