[PATCH 1/3] drm/radeon/r600/r700: only enable CP gui idle interrupts after CP is set up

[Alex Deucher]

Necessary for proper gfx/rlc/smu handshaking.

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
Cc: stable at vger.kernel.org
---
 drivers/gpu/drm/radeon/r600.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 4ea5b10..0bc39cd 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2710,6 +2710,22 @@ int r600_cp_start(struct radeon_device *rdev)
        return 0;
 }

+static void r600_enable_gui_idle_interrupt(struct radeon_device *rdev,
+                                          bool enable)
+{
+       u32 tmp = RREG32(CP_INT_CNTL);
+
+       if (enable)
+               tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
+       else
+               tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
+       WREG32(CP_INT_CNTL, tmp);
+
+       if (!enable)
+               /* read a gfx register */
+               tmp = RREG32(R_028010_DB_DEPTH_INFO);
+}
+
 int r600_cp_resume(struct radeon_device *rdev)
 {
        struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
@@ -2723,6 +2739,8 @@ int r600_cp_resume(struct radeon_device *rdev)
        mdelay(15);
        WREG32(GRBM_SOFT_RESET, 0);

+       r600_enable_gui_idle_interrupt(rdev, false);
+
        /* Set ring buffer size */
        rb_bufsz = order_base_2(ring->ring_size / 8);
        tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
@@ -2768,6 +2786,8 @@ int r600_cp_resume(struct radeon_device *rdev)
                return r;
        }

+       r600_enable_gui_idle_interrupt(rdev, true);
+
        if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
                radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);

@@ -3573,7 +3593,7 @@ static void r600_disable_interrupt_state(struct 
radeon_device *rdev)
 {
        u32 tmp;

-       WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
+       WREG32(CP_INT_CNTL, 0);
        tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
        WREG32(DMA_CNTL, tmp);
        WREG32(GRBM_INT_CNTL, 0);
@@ -3714,7 +3734,7 @@ void r600_irq_fini(struct radeon_device *rdev)

 int r600_irq_set(struct radeon_device *rdev)
 {
-       u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
+       u32 cp_int_cntl;
        u32 mode_int = 0;
        u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
        u32 grbm_int_cntl = 0;
@@ -3734,6 +3754,8 @@ int r600_irq_set(struct radeon_device *rdev)
                return 0;
        }

+       cp_int_cntl = RREG32(CP_INT_CNTL) & ~(RB_INT_ENABLE | 
TIME_STAMP_INT_ENABLE);
+
        if (ASIC_IS_DCE3(rdev)) {
                hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
                hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
-- 
1.8.3.1