On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote: > Signed-off-by: Jani Nikula <jani.nikula at intel.com> > --- > include/drm/drm_dp_helper.h | 95 > ++++++++++++++++++++++++++++++++++++++++++--- > 1 file changed, 90 insertions(+), 5 deletions(-) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 98fefe45d158..209c5b91b0e8 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -92,6 +92,15 @@ > # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ > # define DP_OUI_SUPPORT (1 << 7) > > +#define DP_RECEIVE_PORT_0_CAP_0 0x008 /* XXX 1.2? */ This is part of DPv1.1 as well, the 1.2 in comment stands for DP version? > +# define DP_LOCAL_EDID_PRESENT (1 << 1) > +# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) > + > +#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 > + > +#define DP_RECEIVE_PORT_1_CAP_0 0x00a > +#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b > + > #define DP_I2C_SPEED_CAP 0x00c /* DPI */ > # define DP_I2C_SPEED_1K 0x01 > # define DP_I2C_SPEED_5K 0x02 > @@ -101,10 +110,16 @@ > # define DP_I2C_SPEED_1M 0x20 > > #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ > +# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) > +# define DP_FRAMING_CHANGE_CAP (1 << 1) > # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher > */ > > #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ > > +#define DP_ADAPTER_CAP 0x00f /* 1.2 */ > +# define DP_FORCE_LOAD_SENSE_CAP (1 << 0) > +# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) > + > #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ > # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit > little-endian */ > > @@ -115,6 +130,44 @@ > #define DP_MSTM_CAP 0x021 /* 1.2 */ > # define DP_MST_CAP (1 << 0) > > +#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ > + > +/* AV_SYNC_DATA_BLOCK 1.2 */ > +#define DP_AV_GRANULARITY 0x023 > +# define DP_AG_FACTOR_MASK (0xf << 0) > +# define DP_AG_FACTOR_3MS (0 << 0) > +# define DP_AG_FACTOR_2MS (1 << 0) > +# define DP_AG_FACTOR_1MS (2 << 0) > +# define DP_AG_FACTOR_500US (3 << 0) > +# define DP_AG_FACTOR_200US (4 << 0) > +# define DP_AG_FACTOR_100US (5 << 0) > +# define DP_AG_FACTOR_10US (6 << 0) > +# define DP_AG_FACTOR_1US (7 << 0) > +# define DP_VG_FACTOR_MASK (0xf << 4) > +# define DP_VG_FACTOR_3MS (0 << 4) > +# define DP_VG_FACTOR_2MS (1 << 4) > +# define DP_VG_FACTOR_1MS (2 << 4) > +# define DP_VG_FACTOR_500US (3 << 4) > +# define DP_VG_FACTOR_200US (4 << 4) > +# define DP_VG_FACTOR_100US (5 << 4) > + > +#define DP_AUD_DEC_LAT0 0x024 > +#define DP_AUD_DEC_LAT1 0x025 > + > +#define DP_AUD_PP_LAT0 0x026 > +#define DP_AUD_PP_LAT1 0x027 > + > +#define DP_VID_INTER_LAT 0x028 > + > +#define DP_VID_PROG_LAT 0x029 > + > +#define DP_REP_LAT 0x02a > + > +#define DP_AUD_DEL_INS0 0x02b > +#define DP_AUD_DEL_INS1 0x02c > +#define DP_AUD_DEL_INS2 0x02d > +/* End of AV_SYNC_DATA_BLOCK */ > + > #define DP_GUID 0x030 /* 1.2 */ > > #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ > @@ -173,11 +226,12 @@ > # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ > # define DP_TRAINING_PATTERN_MASK 0x3 > > -# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) > -# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) > -# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) > -# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) > -# define DP_LINK_QUAL_PATTERN_MASK (3 << 2) > +/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ > +# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) > +# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) > +# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) > +# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) > +# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) > > # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) > # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) > @@ -220,14 +274,45 @@ > /* bitmask as for DP_I2C_SPEED_CAP */ > > #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ > +# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) > +# define DP_FRAMING_CHANGE_ENABLE (1 << 1) > +# define DP_PANEL_SELF_TEST_ENABLE (1 << 7) > + > +#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ > +#define DP_LINK_QUAL_LANE1_SET 0x10c > +#define DP_LINK_QUAL_LANE2_SET 0x10d > +#define DP_LINK_QUAL_LANE3_SET 0x10e > +# define DP_LINK_QUAL_PATTERN_DISABLE 0 > +# define DP_LINK_QUAL_PATTERN_D10_2 1 > +# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 > +# define DP_LINK_QUAL_PATTERN_PRBS7 3 > +# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 > +# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 > +# define DP_LINK_QUAL_PATTERN_MASK 7 > + > +#define DP_TRAINING_LANE0_1_SET2 0x10f > +# define DP_LANE0_POST_CURSOR2_SET_MASK (3 << 0) > +# define DP_LANE0_MAX_POST_CURSOR2_REACHED (1 << 2) > +# define DP_LANE1_POST_CURSOR2_SET_MASK (3 << 4) > +# define DP_LANE1_MAX_POST_CURSOR2_REACHED (1 << 6) > + > +#define DP_TRAINING_LANE2_3_SET2 0x110 > +/* bits as in DP_TRAINING_LANE0_1_SET2, but for lanes 2 and 3 */ > Since bits are same, do you want to add 2 and 3 to the corresponding macro above? You can take a call. > #define DP_MSTM_CTRL 0x111 /* 1.2 */ > # define DP_MST_EN (1 << 0) > # define DP_UP_REQ_EN (1 << 1) > # define DP_UPSTREAM_IS_SRC (1 << 2) > > +#define DP_AUDIO_DELAY0 0x112 /* 1.2 */ > +#define DP_AUDIO_DELAY1 0x113 > +#define DP_AUDIO_DELAY2 0x114 > + > #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ > > +#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ > +# define DP_PWR_NOT_NEEDED (1 << 0) > + > #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ > # define DP_PSR_ENABLE (1 << 0) > # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) Some cosmetic comments.
Reviewed-by: Sonika Jindal <sonika.jindal at intel.com>
