On Thu, Aug 06, 2015 at 10:08:17PM +0530, Shashank Sharma wrote:
> From: Kausal Malladi <kausalmalladi at gmail.com>
> 
> I915 driver registers gamma correction as palette correction
> property with DRM layer. This patch adds set_property() and get_property()
> handlers for pipe level gamma correction.
> 
> The set function attaches the Gamma correction blob to CRTC state, these
> values will be committed during atomic commit.
> 
> Signed-off-by: Shashank Sharma <shashank.sharma at intel.com>
> Signed-off-by: Kausal Malladi <kausalmalladi at gmail.com>
> ---
>  drivers/gpu/drm/i915/intel_atomic.c        | 14 ++++++++++++++
>  drivers/gpu/drm/i915/intel_color_manager.c | 20 ++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h           |  3 +++
>  3 files changed, 37 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
> b/drivers/gpu/drm/i915/intel_atomic.c
> index 8d04ee8..9f55e6c 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -324,6 +324,13 @@ int intel_crtc_atomic_set_property(struct drm_crtc *crtc,
>                                  struct drm_property *property,
>                                  uint64_t val)
>  {
> +     struct drm_device *dev = crtc->dev;
> +     struct drm_mode_config *config = &dev->mode_config;
> +
> +     if (property == config->cm_palette_after_ctm_property)
> +             return intel_color_manager_set_pipe_gamma(dev, state,
> +                             &crtc->base, val);
> +
>       DRM_DEBUG_KMS("Unknown crtc property '%s'\n", property->name);
>       return -EINVAL;
>  }
> @@ -333,5 +340,12 @@ int intel_crtc_atomic_get_property(struct drm_crtc *crtc,
>                                  struct drm_property *property,
>                                  uint64_t *val)
>  {
> +     struct drm_device *dev = crtc->dev;
> +     struct drm_mode_config *config = &dev->mode_config;
> +
> +     if (property == config->cm_palette_after_ctm_property)
> +             *val = (state->palette_after_ctm_blob) ?
> +                     state->palette_after_ctm_blob->base.id : 0;
> +
>       return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_color_manager.c 
> b/drivers/gpu/drm/i915/intel_color_manager.c
> index 1c9c477..9a6126c 100644
> --- a/drivers/gpu/drm/i915/intel_color_manager.c
> +++ b/drivers/gpu/drm/i915/intel_color_manager.c
> @@ -27,6 +27,26 @@
>  
>  #include "intel_color_manager.h"
>  
> +int intel_color_manager_set_pipe_gamma(struct drm_device *dev,
> +             struct drm_crtc_state *crtc_state,
> +             struct drm_mode_object *obj, uint32_t blob_id)
> +{
> +     struct drm_property_blob *blob;
> +
> +     blob = drm_property_lookup_blob(dev, blob_id);
> +     if (!blob) {
> +             DRM_ERROR("Invalid Blob ID\n");

A user can trigger this error on demand, so I think we want to keep this
as DRM_DEBUG_KMS (same on patches #10 and 13).


Matt

> +             return -EINVAL;
> +     }
> +
> +     if (crtc_state->palette_after_ctm_blob)
> +             
> drm_property_unreference_blob(crtc_state->palette_after_ctm_blob);
> +
> +     /* Attach the blob to be commited in state */
> +     crtc_state->palette_after_ctm_blob = blob;
> +     return 0;
> +}
> +
>  int get_chv_pipe_gamma_capabilities(struct drm_device *dev,
>               struct drm_palette_caps *palette_caps, struct drm_crtc *crtc)
>  {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index dee5f91..820ded7 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1441,5 +1441,8 @@ extern const struct drm_plane_helper_funcs 
> intel_plane_helper_funcs;
>  /* intel_color_manager.c */
>  void intel_attach_color_properties_to_crtc(struct drm_device *dev,
>               struct drm_mode_object *mode_obj);
> +int intel_color_manager_set_pipe_gamma(struct drm_device *dev,
> +             struct drm_crtc_state *crtc_state,
> +             struct drm_mode_object *obj, uint32_t blob_id);
>  
>  #endif /* __INTEL_DRV_H__ */
> -- 
> 1.9.1
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795

Reply via email to