From: Thierry Reding <tred...@nvidia.com>
Store capabilities in max_* fields and add separate fields for the
currently selected settings.
Signed-off-by: Thierry Reding <treding at nvidia.com>
---
drivers/gpu/drm/drm_dp_helper.c | 35 +++++++++++++++++++++--------------
drivers/gpu/drm/msm/edp/edp_ctrl.c | 6 +++---
drivers/gpu/drm/tegra/dpaux.c | 8 ++++----
drivers/gpu/drm/tegra/sor.c | 28 ++++++++++++++--------------
include/drm/drm_dp_helper.h | 6 ++++--
5 files changed, 46 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index ea74884c9cb3..2f35aba8ef17 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -445,10 +445,13 @@ static void drm_dp_link_reset(struct drm_dp_link *link)
link->revision = 0;
link->edp = 0;
- link->rate = 0;
- link->num_lanes = 0;
+ link->max_lanes = 0;
+ link->max_rate = 0;
link->capabilities = 0;
link->aux_rd_interval = 0;
+
+ link->lanes = 0;
+ link->rate = 0;
}
/**
@@ -474,8 +477,8 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct
drm_dp_link *link)
return err;
link->revision = values[0];
- link->rate = drm_dp_bw_code_to_link_rate(values[1]);
- link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
+ link->max_rate = drm_dp_bw_code_to_link_rate(values[1]);
+ link->max_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
if (link->revision >= 0x11)
if (values[2] & DP_ENHANCED_FRAME_CAP)
@@ -525,6 +528,10 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct
drm_dp_link *link)
/* DP_TRAINING_AUX_RD_INTERVAL is in units of 4 milliseconds */
link->aux_rd_interval = values[14] * 4000;
+ /* use highest available configuration by default */
+ link->lanes = link->max_lanes;
+ link->rate = link->max_rate;
+
return 0;
}
EXPORT_SYMBOL(drm_dp_link_probe);
@@ -619,7 +626,7 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct
drm_dp_link *link)
}
values[0] = drm_dp_link_rate_to_bw_code(link->rate);
- values[1] = link->num_lanes;
+ values[1] = link->lanes;
if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
@@ -936,7 +943,7 @@ static bool drm_dp_link_train_valid(const struct
drm_dp_link_train *train)
static int drm_dp_link_apply_training(struct drm_dp_link *link)
{
struct drm_dp_link_train_set *request = &link->train.request;
- unsigned int lanes = link->num_lanes, *vs, *pe, *pc, i;
+ unsigned int lanes = link->lanes, *vs, *pe, *pc, i;
struct drm_dp_aux *aux = link->aux;
u8 values[4], pattern = 0;
int err;
@@ -1024,7 +1031,7 @@ static void drm_dp_link_get_adjustments(struct
drm_dp_link *link,
struct drm_dp_link_train_set *adjust = &link->train.adjust;
unsigned int i;
- for (i = 0; i < link->num_lanes; i++) {
+ for (i = 0; i < link->lanes; i++) {
adjust->voltage_swing[i] =
drm_dp_get_adjust_request_voltage(status, i) >>
DP_TRAIN_VOLTAGE_SWING_SHIFT;
@@ -1074,7 +1081,7 @@ static int drm_dp_link_recover_clock(struct drm_dp_link
*link)
return err;
}
- if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
+ if (!drm_dp_clock_recovery_ok(status, link->lanes))
drm_dp_link_get_adjustments(link, status);
else
link->train.clock_recovered = true;
@@ -1124,13 +1131,13 @@ static int drm_dp_link_equalize_channel(struct
drm_dp_link *link)
return err;
}
- if (!drm_dp_clock_recovery_ok(status, link->num_lanes)) {
+ if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
DRM_ERROR("clock recovery lost while equalizing channel\n");
link->train.clock_recovered = false;
return 0;
}
- if (!drm_dp_channel_eq_ok(status, link->num_lanes))
+ if (!drm_dp_channel_eq_ok(status, link->lanes))
drm_dp_link_get_adjustments(link, status);
else
link->train.channel_equalized = true;
@@ -1200,7 +1207,7 @@ static int drm_dp_link_train_full(struct drm_dp_link
*link)
retry:
DRM_DEBUG_KMS("full-training link: %u lane%s at %u MHz\n",
- link->num_lanes, (link->num_lanes > 1) ? "s" : "",
+ link->lanes, (link->lanes > 1) ? "s" : "",
link->rate / 100);
err = drm_dp_link_configure(link->aux, link);
@@ -1256,7 +1263,7 @@ static int drm_dp_link_train_fast(struct drm_dp_link
*link)
int err;
DRM_DEBUG_KMS("fast-training link: %u lane%s at %u MHz\n",
- link->num_lanes, (link->num_lanes > 1) ? "s" : "",
+ link->lanes, (link->lanes > 1) ? "s" : "",
link->rate / 100);
err = drm_dp_link_configure(link->aux, link);
@@ -1292,12 +1299,12 @@ static int drm_dp_link_train_fast(struct drm_dp_link
*link)
goto out;
}
- if (!drm_dp_clock_recovery_ok(status, link->num_lanes)) {
+ if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
DRM_ERROR("clock recovery failed\n");
err = -EIO;
}
- if (!drm_dp_channel_eq_ok(status, link->num_lanes)) {
+ if (!drm_dp_channel_eq_ok(status, link->lanes)) {
DRM_ERROR("channel equalization failed\n");
err = -EIO;
}
diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c
b/drivers/gpu/drm/msm/edp/edp_ctrl.c
index 81200e9be382..28e3726999d3 100644
--- a/drivers/gpu/drm/msm/edp/edp_ctrl.c
+++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c
@@ -416,7 +416,7 @@ static void edp_fill_link_cfg(struct edp_ctrl *ctrl)
u32 prate;
u32 lrate;
u32 bpp;
- u8 max_lane = ctrl->dp_link.num_lanes;
+ u8 max_lane = ctrl->dp_link.max_lanes;
u8 lane;
prate = ctrl->pixel_rate;
@@ -714,7 +714,7 @@ static int edp_link_rate_down_shift(struct edp_ctrl *ctrl)
rate = ctrl->link_rate;
lane = ctrl->lane_cnt;
- max_lane = ctrl->dp_link.num_lanes;
+ max_lane = ctrl->dp_link.lanes;
bpp = ctrl->color_depth * 3;
prate = ctrl->pixel_rate;
@@ -772,7 +772,7 @@ static int edp_do_link_train(struct edp_ctrl *ctrl)
* Set the current link rate and lane cnt to panel. They may have been
* adjusted and the values are different from them in DPCD CAP
*/
- dp_link.num_lanes = ctrl->lane_cnt;
+ dp_link.lanes = ctrl->lane_cnt;
dp_link.rate = drm_dp_bw_code_to_link_rate(ctrl->link_rate);
dp_link.capabilities = ctrl->dp_link.capabilities;
if (drm_dp_link_configure(ctrl->drm_aux, &dp_link) < 0)
diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index 07b26972f487..59ec6e57ae6a 100644
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -528,14 +528,14 @@ int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct
drm_dp_link *link,
if (tp == DP_TRAINING_PATTERN_DISABLE)
return 0;
- for (i = 0; i < link->num_lanes; i++)
+ for (i = 0; i < link->lanes; i++)
values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
DP_TRAIN_PRE_EMPH_LEVEL_0 |
DP_TRAIN_MAX_SWING_REACHED |
DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values,
- link->num_lanes);
+ link->lanes);
if (err < 0)
return err;
@@ -547,13 +547,13 @@ int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct
drm_dp_link *link,
switch (tp) {
case DP_TRAINING_PATTERN_1:
- if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
+ if (!drm_dp_clock_recovery_ok(status, link->lanes))
return -EAGAIN;
break;
case DP_TRAINING_PATTERN_2:
- if (!drm_dp_channel_eq_ok(status, link->num_lanes))
+ if (!drm_dp_channel_eq_ok(status, link->lanes))
return -EAGAIN;
break;
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index ee8ad0d4a0f2..fb1f830fb973 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -133,7 +133,7 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
if (err < 0)
return err;
- for (i = 0, value = 0; i < link->num_lanes; i++) {
+ for (i = 0, value = 0; i < link->lanes; i++) {
unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
SOR_DP_TPG_SCRAMBLER_NONE |
SOR_DP_TPG_PATTERN_TRAIN1;
@@ -154,7 +154,7 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
value |= SOR_DP_SPARE_MACRO_SOR_CLK;
tegra_sor_writel(sor, value, SOR_DP_SPARE_0);
- for (i = 0, value = 0; i < link->num_lanes; i++) {
+ for (i = 0, value = 0; i < link->lanes; i++) {
unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
SOR_DP_TPG_SCRAMBLER_NONE |
SOR_DP_TPG_PATTERN_TRAIN2;
@@ -169,7 +169,7 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
if (err < 0)
return err;
- for (i = 0, value = 0; i < link->num_lanes; i++) {
+ for (i = 0, value = 0; i < link->lanes; i++) {
unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
SOR_DP_TPG_SCRAMBLER_GALIOS |
SOR_DP_TPG_PATTERN_NONE;
@@ -396,11 +396,11 @@ static int tegra_sor_calc_config(struct tegra_sor *sor,
u32 num_syms_per_line;
unsigned int i;
- if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
+ if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
return -EINVAL;
- output = link_rate * 8 * link->num_lanes;
input = pclk * config->bits_per_pixel;
+ output = link_rate * 8 * link->lanes;
if (input >= output)
return -ERANGE;
@@ -443,7 +443,7 @@ static int tegra_sor_calc_config(struct tegra_sor *sor,
watermark = div_u64(watermark + params.error, f);
config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
- (link->num_lanes * 8);
+ (link->lanes * 8);
if (config->watermark > 30) {
config->watermark = 30;
@@ -463,12 +463,12 @@ static int tegra_sor_calc_config(struct tegra_sor *sor,
if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
config->hblank_symbols -= 3;
- config->hblank_symbols -= 12 / link->num_lanes;
+ config->hblank_symbols -= 12 / link->lanes;
/* compute the number of symbols per vertical blanking interval */
num = (mode->hdisplay - 25) * link_rate;
config->vblank_symbols = div_u64(num, pclk);
- config->vblank_symbols -= 36 / link->num_lanes + 4;
+ config->vblank_symbols -= 36 / link->lanes + 4;
dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
config->vblank_symbols);
@@ -1100,17 +1100,17 @@ static void tegra_sor_encoder_mode_set(struct
drm_encoder *encoder,
/* power DP lanes */
value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
- if (link.num_lanes <= 2)
+ if (link.lanes <= 2)
value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
else
value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
- if (link.num_lanes <= 1)
+ if (link.lanes <= 1)
value &= ~SOR_DP_PADCTL_PD_TXD_1;
else
value |= SOR_DP_PADCTL_PD_TXD_1;
- if (link.num_lanes == 0)
+ if (link.lanes == 0)
value &= ~SOR_DP_PADCTL_PD_TXD_0;
else
value |= SOR_DP_PADCTL_PD_TXD_0;
@@ -1119,7 +1119,7 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder
*encoder,
value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
- value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
+ value |= SOR_DP_LINKCTL_LANE_COUNT(link.lanes);
tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
/* start lane sequencer */
@@ -1219,7 +1219,7 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder
*encoder,
}
rate = drm_dp_link_rate_to_bw_code(link.rate);
- lanes = link.num_lanes;
+ lanes = link.lanes;
value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
@@ -1237,7 +1237,7 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder
*encoder,
/* disable training pattern generator */
- for (i = 0; i < link.num_lanes; i++) {
+ for (i = 0; i < lanes; i++) {
unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
SOR_DP_TPG_SCRAMBLER_GALIOS |
SOR_DP_TPG_PATTERN_NONE;
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 089d274f857d..521f9d75771d 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -807,8 +807,8 @@ struct drm_dp_link_ops {
struct drm_dp_link {
unsigned char revision;
unsigned char edp;
- unsigned int rate;
- unsigned int num_lanes;
+ unsigned int max_lanes;
+ unsigned int max_rate;
unsigned long capabilities;
unsigned long aux_rd_interval;
@@ -816,6 +816,8 @@ struct drm_dp_link {
struct drm_dp_aux *aux;
struct drm_dp_link_train train;
+ unsigned int lanes;
+ unsigned int rate;
};
int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
--
2.4.5
