[PATCH v5 09/12] drm/exynos: dsi: add the backward compatibility for the renamed clock

[Hyungwon Hwang]

>From the commit a45abd04a46048a4956408543cdbdd8bdedd3215
("drm/exynos: dsi: rename pll_clk to sclk_clk'), the compiled dtb
which contains 'pll_clk' becomes not compatible with the current DSI
driver. This patch adds the backward compatibility for this issue.

Signed-off-by: Hyungwon Hwang <human.hwang at samsung.com>
---
Changes for v5:
- Newly added
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 5f03680..ddcb77e 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -211,6 +211,8 @@
                                        REG_ADDR((dsi), (reg_idx)))
 #define DSI_READ(dsi, reg_idx)         readl(REG_ADDR((dsi), (reg_idx)))

+#define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
+
 static char *clk_names[5] = { "bus_clk", "sclk_mipi",
        "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0",
        "sclk_rgb_vclk_to_dsim0" };
@@ -1866,6 +1868,12 @@ static int exynos_dsi_probe(struct platform_device *pdev)
        for (i = 0; i < dsi->driver_data->num_clks; i++) {
                dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
                if (IS_ERR(dsi->clks[i])) {
+                       if (strcmp(clk_names[i], "sclk_mipi") == 0) {
+                               strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME);
+                               i--;
+                               continue;
+                       }
+
                        dev_info(dev, "failed to get the clock: %s\n",
                                                                clk_names[i]);
                        ret = PTR_ERR(dsi->clks[i]);
--
1.9.1