[PATCH RFC 063/111] staging: etnaviv: add workarounds for GC320 on iMX6

[Lucas Stach]

From: Russell King <rmk+ker...@arm.linux.org.uk>

Add the workarounds found in the GALCORE code (and found to be required)
for the GC320 2D core found on iMX6 to etnaviv.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/staging/etnaviv/etnaviv_gpu.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/staging/etnaviv/etnaviv_gpu.c 
b/drivers/staging/etnaviv/etnaviv_gpu.c
index f2ce3c71e583..92a28f11bab6 100644
--- a/drivers/staging/etnaviv/etnaviv_gpu.c
+++ b/drivers/staging/etnaviv/etnaviv_gpu.c
@@ -393,6 +393,30 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
        if (ret)
                return ret;

+       if (gpu->identity.model == chipModel_GC320 &&
+           gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400 &&
+           (gpu->identity.revision == 0x5007 ||
+            gpu->identity.revision == 0x5220)) {
+               u32 mc_memory_debug;
+
+               mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
+
+               if (gpu->identity.revision == 0x5007)
+                       mc_memory_debug |= 0x0c;
+               else
+                       mc_memory_debug |= 0x08;
+
+               gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
+       }
+
+       /*
+        * Update GPU AXI cache atttribute to "cacheable, no allocate".
+        * This is necessary to prevent the iMX6 SoC locking up.
+        */
+       gpu_write(gpu, VIVS_HI_AXI_CONFIG,
+                 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
+                 VIVS_HI_AXI_CONFIG_ARCACHE(2));
+
        /* set base addresses */
        gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, 0x0);
        gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, 0x0);
-- 
2.1.4