Select pll3_usb_otg for ldb_di clock for rev 1.0 chips.

Signed-off-by: Jiada Wang <jiada_wang at mentor.com>
Signed-off-by: Steve Longerbeam <steve_longerbeam at mentor.com>
---
 arch/arm/mach-imx/clk-imx6q.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 86b58fc..68064a6 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -481,6 +481,9 @@ static void __init imx6q_clocks_init(struct device_node 
*ccm_node)
            cpu_is_imx6dl()) {
                clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], 
clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
                clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], 
clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+       } else {
+               clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], 
clk[IMX6QDL_CLK_PLL3_USB_OTG]);
+               clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], 
clk[IMX6QDL_CLK_PLL3_USB_OTG]);
        }

        clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], 
clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
-- 
1.7.9.5

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