The code currently rounds up the clock to the next MHZ, which is
rounding up a 69.5MHz clock to 70MHz on my machine. This in turn
prevents the display from syncing. Removing this rounding fixes eDP
for me.
Signed-off-by: St?phane Marchesin <marcheu at chromium.org>
---
drivers/gpu/drm/tegra/sor.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 49ef572..75b8690 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -863,19 +863,16 @@ static int tegra_output_sor_setup_clock(struct
tegra_output *output,
struct tegra_sor *sor = to_sor(output);
int err;
- /* round to next MHz */
- pclk = DIV_ROUND_UP(pclk / 2, 1000000) * 1000000;
-
err = clk_set_parent(clk, sor->clk_parent);
if (err < 0) {
dev_err(sor->dev, "failed to set parent clock: %d\n", err);
return err;
}
- err = clk_set_rate(sor->clk_parent, pclk);
+ err = clk_set_rate(sor->clk_parent, pclk / 2);
if (err < 0) {
dev_err(sor->dev, "failed to set base clock rate to %lu Hz\n",
- pclk * 2);
+ pclk);
return err;
}
--
1.9.1.423.g4596e3a
