[PATCH 2/3] drm/radeon: Use write-combined CPU mappings of IBs on >= CIK

[Michel Dänzer]

From: Michel D?nzer <michel.daen...@amd.com>

Signed-off-by: Michel D?nzer <michel.daenzer at amd.com>
---
 drivers/gpu/drm/radeon/radeon_ring.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_ring.c 
b/drivers/gpu/drm/radeon/radeon_ring.c
index 7cfea7e..20b0e4f 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -201,10 +201,22 @@ int radeon_ib_pool_init(struct radeon_device *rdev)
        if (rdev->ib_pool_ready) {
                return 0;
        }
-       r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
-                                     RADEON_IB_POOL_SIZE*64*1024,
-                                     RADEON_GPU_PAGE_SIZE,
-                                     RADEON_GEM_DOMAIN_GTT, 0);
+
+       if (rdev->family >= CHIP_BONAIRE) {
+               r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
+                                             RADEON_IB_POOL_SIZE*64*1024,
+                                             RADEON_GPU_PAGE_SIZE,
+                                             RADEON_GEM_DOMAIN_GTT,
+                                             RADEON_GEM_GTT_WC);
+       } else {
+               /* Before CIK, it's better to stick to cacheable GTT due
+                * to the command stream checking
+                */
+               r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
+                                             RADEON_IB_POOL_SIZE*64*1024,
+                                             RADEON_GPU_PAGE_SIZE,
+                                             RADEON_GEM_DOMAIN_GTT, 0);
+       }
        if (r) {
                return r;
        }
-- 
2.0.1