Hi all, I post a report to illustrate the structure of the Verilog simulation block, you can find it here<https://b0wen-hu.github.io/2019/05/29/GSoC-Structure-of-the-Verilog-simulation-block/>(https://b0wen-hu.github.io/2019/05/29/GSoC-Structure-of-the-Verilog-simulation-block/).
You can find it in the report, that there are a lot of routines should be done in the constructor of the block. There might be errors in these routines whether during compiling the Verilog file or generating shred library. I wonder what kind of behavior should this block have when something goes wrong in the constructor. The Interface of external shared library is still undetermined. I think there should be a function that could control every single port of the Verilog module. I plan to store the port map with std::unordered_map<(std::string) Port_name, pair<(unsigned int) Offset, (unsigned int) Port_value>>. Please feel free to let me know if you have any questions or suggestions. Best regards, Bowen
_______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org https://lists.gnu.org/mailman/listinfo/discuss-gnuradio
