On Tue, Mar 19, 2019 at 02:06:36PM +0000, Bowen Hu wrote: > Hi all, > Thanks Marcus for giving me good advice. I implemented a demo of plugin > structure( https://github.com/B0WEN-HU/Plugin-demo ), which can compile > and execute C++ code at runtime. > My proposal draft has been posted here( > https://github.com/B0WEN-HU/GSoC-19-Proposal/blob/master/Proposal.md ). > Here are two questions that need to be discussed, I suppose, in this > proposal. They are as follows, and also included in the proposal. > >Users might want to specify the rules of data conversion in case that the > default conversion rules won't work properly. I wonder whether it is a > part of the job? > >Due to cycle-accurate Verilog simulation by Verilator, the timing of > input and output may vary in different module. For example, there might be > uncertain number of cycles before the output data is valid(However, the > author of the module should know about it).Or, some module would have to > take its time to do the calculation, and won't respond to the input data > for several cycles, which means if we put the data to the input port > during these cycles, the data would just be ignored. This information > should be informed by user through some mechanisms. Moreover, I noticed > that there are different types of blocks in GNU Radio such as decimators > and Interpolators, and I wonder whether it is possible to implement the > functions mentioned above without recompiling the block for different > Verilog modules. > I would be very grateful if you could give me some suggestions. Please do > let me know if there are any mistakes.
Thanks for the nice proposal! Can you please re-read the student instructions, we want to make sure you've read *all* of them. They contain some instructions to update your proposal accordingly. -- M
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