Hello everyone,
I am using a USRP X310 with basic RX and basic TX daughterboards and I
would like to know the exact relation between the number I enter as a
parameter for the central frequency in the UHD USRP sink/source block
(which is a real number) and the actual phase per each sample.
As a matter of facts, if the DDC/DUC chains were using a DDS, the
relation would be pretty straightforward (knowing the control word of
the DDS and the number of bits of the phase accumulator...). However, as
I understand, the FPGA design uses a CORDIC for the DDC/DUC chain, for
which the exact correspondence between sample index and phase is not as
straight forward to derive. I am sorry if this is textbook material for
CORDIC specialists (which I am not...), but I am wondering if someone
could point me to the exact formula of phase vs sample index that I
could use to very accurately know what is going on in the DDC/DUC chain.
The bottom line is that I need to be sure of what is happening at the
nrad level for MHz-ish input/output and mod/demod frequency, and the
intricacies of the CORDIC behavior is - to my best understanding -
playing a major role at this level.
Any help would be greatly appreciated.
Best regards,
Nicolas
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