>From a CPU and thus, SDR _software_ throughput, point of view, the E310
certainly isn't more powerful than a modern laptop + B2xx; latency might
be a bit shorter, though, but in the end, you're making the most
important point here:

If you need to eradicate the nondeterministic behaviour of general
purpose operating systems running on general purpose computing hardware
(such as Linux or Windows on a PC or the Zynq's ARM), you can only do
two things:

1. Have enough leeway for timing, so that you're *always* faster than
you need to be, or

2. doing the timing-sensitive stuff directly on dedicated realtime
environments, which in this case means the FPGA.

Cheers,

Marcus

On 03/29/2017 10:27 PM, Saulo Queiroz wrote:
> An interesting question is whether more powerful SDR (e.g. E310)
> should manage to do that (DATA+SIFS+ACK).
> RFNoC may facilitate the FPGA design...
>
> 2017-03-29 17:19 GMT-03:00 Bastian Bloessl <[email protected]
> <mailto:[email protected]>>:
>
>     Hi,
>
>     On 03/29/2017 01:11 PM, sumitstop wrote:
>     > Hi,
>     >
>     > With gr-ieee 802.11, I know that SIFS cannot be respected becz
>     of USB delays
>     > (B210), but what we can also try is that : sending ACK packet
>     before all the
>     > layer-2 retries are exhausted ! Instead of sending ACK withing
>     10 microsecs.
>     >
>     > In this way, the throughput will be down for sure but the device can
>     > communicate with a commercial 802.11 AP.
>     >
>     > I was wondering if anyone tried like this and I can get some
>     heads up.
>     >
>
>     It's not only about sending fast enough, but mainly about sending
>     at the
>     right point in time (i.e. immediately after a frame). Since the SDR
>     doesn't do channel sensing on the FPGA, this is at least not
>     straightforward.
>
>     Best,
>     Bastian
>
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>
>
>
>
> -- 
> Saulo Jorge bq
> - "Beware of bugs in the above code; I have only proved it correct,
> not tried it." 
> Donald Knuth.
>
>
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