Hi, Thanks for the detailed reply.
>>>>>>From these I could add noc_block_digital_gain (built successfully) >>>>>>but couldn't add chdr_fifo_large (running make X310_RFNOC_HLS_HG gave an error) >>>>Could you please tell us what error did it throw? I inserted the following code in rfnoc_ce_auto_inst_x310.v file to add chdr_fifo_large: *****************************************************************************************************chdr_fifo_large inst_chdr_fifo_large ( .bus_clk(bus_clk), .bus_rst(bus_rst), .ce_clk(ce_clk), .ce_rst(ce_rst), .i_tdata(ce_o_tdata[5]), .i_tlast(ce_o_tlast[5]), .i_tvalid(ce_o_tvalid[5]), .i_tready(ce_o_tready[5]), .o_tdata(ce_i_tdata[5]), .o_tlast(ce_i_tlast[5]), .o_tvalid(ce_i_tvalid[5]), .o_tready(ce_i_tready[5]), .debug(ce_debug[5]));* **************************************************************************************************** >From your reply I gather that I cannot add chdr_fifo_large block (since only blocks starting with "noc_block_" are allowed) but following is the error I got: ******************************************************************************************************************************************************************************************************** INFO: [Synth 8-256] done synthesizing module 'chdr_fifo_large__parameterized0' (170#1) [/home/vrege/rfnoc/src/uhd-fpga/usrp3_rfnoc/lib/rfnoc/chdr_fifo_large.v:5] ERROR: [Synth 8-448] named port connection 'bus_clk' does not exist for instance 'inst_chdr_fifo_large' of module 'chdr_fifo_large' [/home/vrege/rfnoc/src/uhd-fpga/usrp3_rfnoc/top/x300/rfnoc_ce_auto_inst_x310.v:56] ERROR: [Synth 8-448] named port connection 'bus_rst' does not exist for instance 'inst_chdr_fifo_large' of module 'chdr_fifo_large' [/home/vrege/rfnoc/src/uhd-fpga/usrp3_rfnoc/top/x300/rfnoc_ce_auto_inst_x310.v:56] ERROR: [Synth 8-448] named port connection 'ce_clk' does not exist for instance 'inst_chdr_fifo_large' of module 'chdr_fifo_large' [/home/vrege/rfnoc/src/uhd-fpga/usrp3_rfnoc/top/x300/rfnoc_ce_auto_inst_x310.v:57] ERROR: [Synth 8-448] named port connection 'ce_rst' does not exist for instance 'inst_chdr_fifo_large' of module 'chdr_fifo_large' [/home/vrege/rfnoc/src/uhd-fpga/usrp3_rfnoc/top/x300/rfnoc_ce_auto_inst_x310.v:57] ERROR: [Synth 8-448] named port connection 'debug' does not exist for instance 'inst_chdr_fifo_large' of module 'chdr_fifo_large' [/home/vrege/rfnoc/src/uhd-fpga/usrp3_rfnoc/top/x300/rfnoc_ce_auto_inst_x310.v:60] ... ERROR: [Synth 8-285] failed synthesizing module 'synchronizer_impl__parameterized0' [/home/vrege/rfnoc/src/uhd-fpga/usrp3_rfnoc/lib/control/synchronizer_impl.v:5] ERROR: [Synth 8-285] failed synthesizing module 'synchronizer__parameterized0' [/home/vrege/rfnoc/src/uhd-fpga/usrp3_rfnoc/lib/control/synchronizer.v:5] ERROR: [Synth 8-285] failed synthesizing module 'x300_core' [/home/vrege/rfnoc/src/uhd-fpga/usrp3_rfnoc/top/x300/x300_core.v:2] ERROR: [Synth 8-285] failed synthesizing module 'x300' [/home/vrege/rfnoc/src/uhd-fpga/usrp3_rfnoc/top/x300/x300.v:15] ******************************************************************************************************************************************************************************************************** >>>>In that directory there is an 'addsub' block written in HLS as an example. I want to actually add a custom 'fir' block that I have written in HLS to the built image. So I created another fir_hls directory in the lib/hls folder using the addsub_hls as an example with my own fir_hls.cpp, .tcl and Makefile.inc I also modified the Makefile.inc in the lib/hls folder correspondingly. Then I added "noc_block_fir" to the rfnoc_ce_auto_inst file. On running make X310_RFNOC_HLS_HG I got the following error: ******************************************************************************************************************************************************************************************************** ERROR: [Synth 8-439] module 'noc_block_fir' not found [/home/vrege/rfnoc/src/uhd-fpga/usrp3_rfnoc/top/x300/rfnoc_ce_auto_inst_x310.v:62] ERROR: [Synth 8-285] failed synthesizing module 'x300_core' [/home/vrege/rfnoc/src/uhd-fpga/usrp3_rfnoc/top/x300/x300_core.v:2] ERROR: [Synth 8-285] failed synthesizing module 'x300' [/home/vrege/rfnoc/src/uhd-fpga/usrp3_rfnoc/top/x300/x300.v:15] ******************************************************************************************************************************************************************************************************** So I added the line "noc_block_fir.v \" to the lib/rfnoc/Makefile.srcs file But that gave another error: make[1]: *** No rule to make target `/home/vrege/rfnoc/src/uhd-fpga/usrp3_rfnoc/lib/rfnoc/noc_block_fir.v', needed by `bin'. Stop. What changes do I need to make in the procedure to add my custom FIR block to the image built by make? Thanks, Vishwesh On Wed, Dec 7, 2016 at 12:16 AM, Nicolas Cuervo <nicolas.cue...@ettus.com> wrote: > Hello Vikesh, > > Please take a look at this section of our "Getting started with RFNoC > Development" guide, specifically the "wiring CE" section [1]. As Marcus > stated, NoC blocks start with "noc_block_", and this is the way to identify > them in the sources. > > On 12/06/2016 10:37 PM, Vishwesh Rege wrote: > >>>>What are the list of blocks that I can add? > > In that page that I just referenced there is a list of the current > noc_blocks provided by Ettus. > > >>>>But what functionality do the other FIFOs provide (when am I supposed > to use them)? > >>>>chdr_fifo_large > >>>>noc_block_axi_dma_fifo > >>>>split_stream_fifo > >>>>ram_to_fifo ... etc. > > Talking about "blocks' in a really general way, you'd only have to take in > consideration the 'noc_block_axi_dma_fifo". The others that you listed are > part of the library because the serve other functions at a lower level of > abstraction to generate the blocks that you are going to use directly in > your application. > > >>>>Using the make.py approach: > >>>>From what I understand make.py only generates an output.v file right? > After running make.py do I have to copy the contents of the output.v file > to >>>>rfnoc_ce_auto_inst_x310.v? > > No. make.py will take the blocks that you provided as parameters, and with > that it will generate your rfnoc_ce_auto_inst file and right after will > kick your bitstream build. The script only needs you to have vivado > installed, but you don't have to copy contents of files. It appears that > you gave the script the "-o output.v" option. This will generate a file > without kicking the build, but this option you'd use as a verification of > the file correctness. If you just skip this option, the > rfnoc_ce_auto_inst_x310.v file will be overwritten directly and your build > will start automatically. > > >>>>From these I could add noc_block_digital_gain (built successfully) > >>>>but couldn't add chdr_fifo_large (running make X310_RFNOC_HLS_HG gave > an error) > > Could you please tell us what error did it throw? > > >>>>Finally what difference does it make if I run "make X310_RFNOC_HG" > versus "make X310_RFNOC_HLS_HG" > > The X310_RFNOC_HLS_HG target uses "High Level Synthesis" to generate the > build. This is a way of generating hardware designs by the means of > software algorithms (i.e. you use C, C++ or SystemC to describe your > hardware, and the build system will translate that into hardware). By > selecting this target you are telling the build system that you wrote some > C/C++/SystemC code, located it at usrp3/lib/hls, and you want it to be part > of your design. In that directory there is an 'addsub' block written in HLS > as an example. > > The X310_RFNOC_HG will synthesize your design using verilog sources. > > Cheers, > > - Nicolas > > [1] https://kb.ettus.com/Getting_Started_with_RFNoC_Development#Wiring_up_ > computation_engines_and_building_the_FPGA_image > > > > On Tue, Dec 6, 2016 at 10:45 PM, Marcus Müller <marcus.muel...@ettus.com> > wrote: > >> A NoC block should, as far as I can tell, always start with noc_block_. >> >> >> Best regards, >> >> Marcus >> >> On 12/06/2016 10:37 PM, Vishwesh Rege wrote: >> >> Hi, >> >> What are the list of blocks that I can add? >> >> For example, >> Looking at the list of blocks in usrp3_rfnoc/lib/rfnoc/Makefile.srcs >> >> From these I could add noc_block_digital_gain (built successfully) >> but couldn't add chdr_fifo_large (running make X310_RFNOC_HLS_HG gave an >> error) >> >> How do I know which blocks will work? >> >> For the error I'm getting in GRC "FIFO_0 block missing" I think >> noc_block_axi_fifo_loopback is probably the right one >> But what functionality do the other FIFOs provide (when am I supposed to >> use them)? >> chdr_fifo_large >> noc_block_axi_dma_fifo >> split_stream_fifo >> ram_to_fifo ... etc. >> >> Thanks, >> Vishwesh >> >> -- >> To change the blocks, you need to edit rfnoc_ce_auto_inst_x310.v twice: >> You need to change NUM_CE (at the top), and then the actual block list. >> >> For FIFOs, you can go to the bottom and use the generate for loop to add >> more FIFOs. >> >> You can use make.py to autogenerate this file (in >> usrp3/tools/scripts/make.py). >> >> Cheers, >> Martin >> >> On 12/04/2016 05:55 PM, Vishwesh Rege wrote: >> > Hi, >> > >> > I want to add the FIFO block in usrp3_rfnoc/lib/fifo to USRP along with >> > the addsub module in usrp3_rfnoc/lib/hls folder. >> > >> > I'm running make X310_RFNOC_HLS_HG from usrp3_rfnoc/top/x300 directory >> > and then flashing the generated image in build/. >> > >> > However, the FIFO isn't included in the image for some reason. Only the >> > following RFNoC blocks are actually flashed: >> > | | | * DmaFIFO_0 >> > | | | * Radio_0 >> > | | | * Radio_1 >> > | | | * AddSub_0 >> > | | | * FIR_0 >> > | | | * FFT_0 >> > | | | * Window_0 >> > | | | * NullSrcSink_0 >> > | | | * SigGen_0 >> > | | | * MovingAverage_0 >> > | | | * VectorIIR_0 >> > | | | * KeepOneInN_0 >> > | | | * fosphor_0 >> > >> > The Makefile usrp3_rfnoc/top/x300/Makefile.x300.inc already includes >> > FIFO_SRCS in DESIGN_SRCS >> > >> > Do I need to make any changes to include the FIFO? >> > >> > Any help is appreciated. >> > >> > >> > >> > >> >> >> _______________________________________________ >> Discuss-gnuradio mailing >> listDiscuss-gnuradio@gnu.orghttps://lists.gnu.org/mailman/listinfo/discuss-gnuradio >> >> >> >> _______________________________________________ >> Discuss-gnuradio mailing list >> Discuss-gnuradio@gnu.org >> https://lists.gnu.org/mailman/listinfo/discuss-gnuradio >> >> > -- Vishwesh Rege +1 (858) 729-4157 | vr...@ucsd.edu | https://sites.google.com/site/vishweshrege
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