OK, to be precise {B200|B205|B200mini|B210} should have the same common
base platform in the FPGA including the interface used for the radio. B230
is different.
If wish to understand further the exact significance of the USRP model
numbers I suggest you start here: http://dilbert.com/strip/1992-04-06

On Wed, Apr 13, 2016 at 12:57 PM, Alexander Levedahl <
alexanderleved...@gmail.com> wrote:

> Out of curiosity, when you say B2x0, did you mean to exclude the B205
> mini?
>
> Alex
>
> On Wed, Apr 13, 2016 at 2:16 PM, Ian Buckley <i...@ionconcepts.com> wrote:
>
>> For what (little) it's worth I removed the H/W constraints in B2x0 that
>> forced a minimum of 5MHz master clock rate when UHD 3.9.x was released.
>> Running AD9361 at low clock rates isn't the best way to utilize its
>> capabilities but it may help for certain niche narrow band applications.
>>
>> -Ian
>>
>>
>> On Wed, Apr 13, 2016 at 6:20 AM, Ron Economos <w...@comcast.net> wrote:
>>
>>> Yes. I routinely set it to ((8000000 * 6) / 7) * 4 for DVB-T2
>>> applications.
>>>
>>> Ron
>>>
>>>
>>> On 04/13/2016 08:32 AM, Alexander Levedahl wrote:
>>>
>>> So, it can be set to say 50.3+pi/10MHz?
>>>
>>>
>>> On Wed, Apr 13, 2016 at 10:55 AM, Ron Economos <w...@comcast.net> wrote:
>>>
>>>> Correction. The master clock rate can be set to anything from 5 MHz to
>>>> 56 MHz. The bandwidth is 200 kHz to 56 MHz.
>>>>
>>>> Ron
>>>>
>>>>
>>>> On 04/13/2016 07:46 AM, Ron Economos wrote:
>>>>
>>>>> The B2X0 series has a programmable master clock. You can set it to
>>>>> anything from 200 kHz to 56 MHz.
>>>>>
>>>>> Ron
>>>>>
>>>>> On 04/13/2016 05:55 AM, Alexander Levedahl wrote:
>>>>>
>>>>>> Hello,
>>>>>>
>>>>>> Is there a list of sample rates and associated bandwidths supported
>>>>>> by the B2xx series or a way to generate the list? E.g., the list for the
>>>>>> X310 is to take 120MHz, 184.32MHz, and 200MHz and divide by an integer.
>>>>>>
>>>>>> Thanks,
>>>>>> Alex
>>>>>>
>>>>>>
>>>>>
>>>>
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>>>>
>>>
>>>
>>>
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>>
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