Hi all. I've successfully written a DSSS modulator and demodulator in Windows
with a chip rate of 16x. It writes samples to a file that the demodulator can
read and despread. Before I try any practical implementations, I need to know
how a DSSS stream would be synchronized. Assuming the transmitter and receiver
were perfectly clocked in unison, what stops the receiver from tuning in in the
middle of a byte, thus getting a nibble from the current byte and a nibble from
the next?
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